FlexCAN in MPC5777c

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FlexCAN in MPC5777c

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Contributor III

 I am working on FlexCAN in MPC5777c . Im trying to use the Application note and simple transmit recieve on FlexCAN as example.

On it i have a some clarifications.

1.What is the reason for getting the message Hello in MB4  - Is it the case of the length of the string. Message is being transmiitted on MB[0] and checked on BUF4TO1I and if the length is greater  or equal to 8 in BUF8TO31I . correct me if im wrong.

2. /* wait until FlexCAN ready */
while(1 == CAN_A.MCR.B.FRZACK) {}
while(1 == CAN_A.MCR.B.NOTRDY) {}

What could be the possible reason if the Application is stuck in the above lines is the CAN hardware has an issue?

Thank In Advance,

Vignesh

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Contributor III

Hi Petr,

           Thanks for sharing the calculation sheet. Now what I did was I currently stopped executing the code for

            my target board and started to test on EVB but only with daughter board - standalone.

         I dont have a motherboard. I used similar clock init configuario. Still stuck with that issue in FLEX_CAN_init function with while(1 == CAN_A.MCR.B.FRZACK)

What needs to be changed for EVB used only for daughter board . I checked with jumper settings seems to be right only.

I was able to power up the user LED on daughter board. but I'm stuck in this CAN.

Thanks,

Vignesh

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Contributor III

I'm using CAN A peripherals for communication in daughter board . Please tell me whether that is correct as t says it has only on CAN peripheral on daughter board I thought initialize and the transmitting on CAN A peripheral and check it with probe or at least in debug point whether it leaves the FRZACK. Hope my approach is right correct me if I'm wrong.

Regards,

Vignesh

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NXP TechSupport
NXP TechSupport

Yes, the PowerSBC on the daughter-card has one CAN transceiver and CAN_A module can be connected to it through J506 jumpers. So the communication should be possible if this embedded CAN transceiver is active.

Anyway you can test module pin setting if you disconnect from transceiver and connect TX/RX pins together on J506 jumpers. You should see CAN message send repeatedly due to missing ACK.

BR, Petr

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Contributor III

Hi,

Thanks. ill check and revert you in case of any clarifications.

Regards,

Vignesh

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Contributor III

Hi,

   Ok I shall check it. Could you please explain  how you derived on the CAN settings for control registers

for my configuration

CANx_CTRL1 = 0x04590002;  // bitrate=500kbps, CPI clk=25 MHz; Prescaler= 5, PROPSEG=3, PSEG1=4, PSEG2=2, RJW=2, smp=80%

this configuration how is it calculated it ll be helpful for me for changing values if required

Thanks,

Vignesh

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NXP TechSupport
NXP TechSupport

Hi,

I used below excel tool

https://community.nxp.com/docs/DOC-342618

BR, Petr

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Contributor III

Hi,

    I'm getting stuck with the above said configuration in the init  function for flexCAN for which I have attached test project also. I commented those lines just for a testing purpose to ensure just because its getting stuck because of any delay required

But its getting stuck in the transmit function in the while

while ( CAN_A.IFLAG1.B.BUF31TO8I == 0) { } // wait until the tx is completed.//

Code snippet is pasted below.

void Transmit_CAN_Msg()

/* Assumption: Message buffer CODE is INACTIVE */

/* prepare data to send */

/* prepare data to send */

u8_txdata ^= 0x01; /* toggle bit 0 */

/* CAN_A MB8 Tx Send Once, data length to send = 1 byte */

CAN_A.MB[8].CS.R = 0x08600000; /* Tx INACTIVE + IDE + SRR */

CAN_A.MB[8].ID.R = 0x12340000; /* Ext.ID = 0x12340000 */

CAN_A.MB[8].DATA.B[0] = u8_txdata; /* data to send */

CAN_A.MB[8].CS.R = 0x0C610000; /* send 1 byte, ext.frame */

while ( CAN_A.IFLAG1.B.BUF31TO8I == 0) { } // wait until the tx is completed.

CAN_A.IFLAG1.R = 0x00000100;

Kindly help me out on this issue.

Thanks in Advance,

Vignesh

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NXP TechSupport
NXP TechSupport

Hi,

I see no issue when testing CAN_Test_Project_Z7_0 project on the EVB.

FlexCANs normally leaves Freeze mode and if CAN_A is connected to CAN_B (through tarnsceivers), CAN_A sends message successfully so it passes while ( CAN_A.IFLAG1.B.BUF31TO8I == 0) { }

BR, Petr

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Contributor III

Hi,

   Thanks for testing . the clock that I sent youu I mean system clock was 25 Mhz - XTAL  and the can bit timing part was also what which you had given me for the same CAN_A.CTRL1.R = 0x04590002;

Could you please tell me what were the changes that you made or you had simply used my configuration in EVB.

If that is the case what is the possible reason it could not work in my case

Thanks In Advance,

Vignesh

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NXP TechSupport
NXP TechSupport

Hi, 

I simply used the code as is on the EVB, even if clock config is not right as there is different crystal on the EVB.

You meant you are running system clock from crystal? But the code is using PLL0 for system clock .

For your issue; check the CAN connection on your board and also check CAN registers for expected values.

BR, Petr

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Contributor III

Hi Petr,

            As suggested by you I have uploaded the test project containing only CAN related stuff. Kindly look into it and update me.

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Contributor III

Hi,

   Thanks So in general any MB can be selected for transmission or reception is it?

Thanks

Vignesh

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NXP TechSupport
NXP TechSupport

yes

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Contributor III

Thanks.

One of my other main clarification is I need to communicate between CAN A and CAN B flexcan peripherals. I'm setting pins required for  the transceiver on my target board which has MPC5777c controller.

My clock configuration is 25MHZ and per clck configuration is 100MHZ . My desired baud rate is 500k baud.

Can I use the same configuration used in MPC 5777c example.

static void FlexCAN_A_Init(void)
{
    uint32_t i = 0;
   
    /* enable the FlexCAN module, reset and freeze */
    CAN_A.MCR.R = (0
                    | CAN_MCR_FRZ  /* enabled to enter Freeze mode */
                    | CAN_MCR_HALT /* enter freeze mode if FRZ bit is set */
                    | CAN_MCR_SOFTRST /* soft reset */
                    | CAN_MCR_SRXDIS  /* self reception enabled */
                    | CAN_MCR_BCC  /* individual Rx masking and queue */
                    | 0x0000003F);                     
                   
                   
    /* wait until soft reset completes */
    while(1 == CAN_A.MCR.B.SOFTRST) {};
   
    /* double check that we are actually in freeze mode */
    while(0 == CAN_A.MCR.B.FRZACK) {};
    while(0 == CAN_A.MCR.B.NOTRDY) {};
   
    CAN_A.CR.R = 0x04E40004; /* CAN bus: 40 MHz clksrc, 500K bps with 16 tq */
                              /* PRESDIV+1 = Fclksrc/Ftq = 40 MHz/8MHz = 5 */
                              /*    so PRESDIV = 4 */
                              /* PSEG2 = Phase_Seg2 - 1 = 5 - 1 = 4 */
                              /* PSEG1 = PSEG2 = 4 */
                              /* PROPSEG= Prop_Seg - 1 = 5 - 1 = 4 */
                              /* RJW = Resync Jump Width - 1 = 4 - 1 = 1 */
                              /* SMP = 0: use 1 bit per CAN sample */
                              /* CLKSRC=0 (unchanged): Fcanclk= Fxtal= 40 MHz*/

   // code to disable ECC reporting at all
   CAN_A.CTRL2.B.ECRWRE = 1; // enable editing of MECR
   CAN_A.MECR.B.ECRWRDIS = 0; // enable writes to MECR
   CAN_A.MECR.R = 0x00000100; // disable ECC error ISR and disable ECC at all , keep normal operation
   CAN_A.CTRL2.B.ECRWRE = 0; // lock the MECR again
   
   
    /* Make first 32 message buffers inactive by writing their control fields
       to "not active". They will be left inactive until we're ready for communication. */     
    for(i=0;i<64;i++)
    {
        CAN_A.BUF[i].CS.R = 0;
    }
   
    /* set mask registers - all ID bits must match */
    for(i=0;i<64;i++)
    {
        CAN_A.RXIMR[i].R = 0x1FFFFFFF;
    }

    /* configure CNTX_A and CNRX_A pin functions on PCR83 and PCR84 */
    SIU.PCR[83].R = 0x060C; /* CNTXA, push/pull, max slew rate */
    SIU.PCR[84].R = 0x0503; /* CNRXA, weak pull device disabled */
   
    /* Finally clear the HALT flag in MCR to enable the FlexCAN
     * to synchronize with the CAN bus and allow
     * participation in communication. */
    CAN_A.MCR.B.HALT = 0;
   
    /* wait until FlexCAN ready */
    while(1 == CAN_A.MCR.B.FRZACK) {}
    while(1 == CAN_A.MCR.B.NOTRDY) {}
}

/*******************************************************************************
Function Name : FlexCAN_B_Init
Engineer      : PetrS
Date          : Jul-22-2016
Parameters    : NONE
Modifies      : NONE
Returns       : NONE
Notes         : FlexCAN_B initialization
Issues        : NONE
*******************************************************************************/
static void FlexCAN_B_Init(void)
{
    uint32_t i = 0;
   
    /* enable the FlexCAN module, reset and freeze */
    CAN_B.MCR.R = (0
                    | CAN_MCR_FRZ  /* enabled to enter Freeze mode */
                    | CAN_MCR_HALT /* enter freeze mode if FRZ bit is set */
                    | CAN_MCR_SOFTRST /* soft reset */
                    | CAN_MCR_SRXDIS  /* self reception enabled */
                    | CAN_MCR_BCC  /* individual Rx masking and queue */
                    | 0x0000003F);                     
                   
                   
    /* wait until soft reset completes */
    while(1 == CAN_B.MCR.B.SOFTRST) {};
   
    /* double check that we are actually in freeze mode */
    while(0 == CAN_B.MCR.B.FRZACK) {};
    while(0 == CAN_B.MCR.B.NOTRDY) {};
      
    CAN_B.CR.R = 0x04E40004; /* CAN bus: 40 MHz clksrc, 500K bps with 16 tq */
                              /* PRESDIV+1 = Fclksrc/Ftq = 40 MHz/8MHz = 5 */
                              /*    so PRESDIV = 4 */
                              /* PSEG2 = Phase_Seg2 - 1 = 5 - 1 = 4 */
                              /* PSEG1 = PSEG2 = 4 */
                              /* PROPSEG= Prop_Seg - 1 = 5 - 1 = 4 */
                              /* RJW = Resync Jump Width - 1 = 4 - 1 = 1 */
                              /* SMP = 0: use 1 bit per CAN sample */
                              /* CLKSRC=0 (unchanged): Fcanclk= Fxtal= 40 MHz*/

    // code to disable ECC reporting at all
   CAN_B.CTRL2.B.ECRWRE = 1; // enable editing of MECR
   CAN_B.MECR.B.ECRWRDIS = 0; // enable writes to MECR
   CAN_B.MECR.R = 0x00000100; // disable ECC error ISR and disable ECC at all , keep normal operation
   CAN_B.CTRL2.B.ECRWRE = 0; // lock the MECR again

   
    /* Make first 32 message buffers inactive by writing their control fields
     * to "not active". They will be left
     * inactive until we're ready for communication. */     
    for(i=0;i<64;i++)
    {
        CAN_B.BUF[i].CS.R = 0;
    }
   
    /* set mask registers - all ID bits must match */
    for(i=0;i<64;i++)
    {
        CAN_B.RXIMR[i].R = 0x1FFFFFFF;
    }

    /* configure CNTX_B and CNRX_B pin functions on PCR85 and PCR86 */
    SIU.PCR[85].R = 0x060C; /* CNTXA, push/pull, max slew rate */
    SIU.PCR[86].R = 0x0503; /* CNRXA, weak pull device disabled */
   
    /* Finally clear the HALT flag in MCR to enable the FlexCAN
     * to synchronize with the CAN bus and allow
     * participation in communication. */
    CAN_B.MCR.B.HALT = 0;
   
    /* wait until FlexCAN ready */
    while(1 == CAN_B.MCR.B.FRZACK) {}
    while(1 == CAN_B.MCR.B.NOTRDY) {}
}

I tried with above configuration.

also I tried to change config as below

void FlexCAN_A_Init(void)

{

uint32_t i = 0;

//SIU.GPDO[148].R |= 0;

/* enable the FlexCAN module, reset and freeze */

CAN_A.MCR.R = (0

| CAN_MCR_FRZ /* enabled to enter Freeze mode */

| CAN_MCR_HALT /* enter freeze mode if FRZ bit is set */

| CAN_MCR_SOFTRST /* soft reset */

| CAN_MCR_SRXDIS /* self reception enabled */

| CAN_MCR_BCC /* individual Rx masking and queue */

| 0x0000003F);

 

/* wait until soft reset completes */

while(1 == CAN_A.MCR.B.SOFTRST) {};

/* double check that we are actually in freeze mode */

while(0 == CAN_A.MCR.B.FRZACK) {};

while(0 == CAN_A.MCR.B.NOTRDY) {};

/* CAN bus: 25 MHz clksrc, 300K bps with 16 tq */

/* PRESDIV+1 = Fclksrc/Ftq = 25 MHz/4.8MHz = 5 */

/* so PRESDIV = 4 */

/* PSEG2 = Phase_Seg2 - 1 = 5 - 1 = 4 */

/* PSEG1 = PSEG2 = 4 */

/* PROPSEG= Prop_Seg - 1 = 5 - 1 = 4 */

/* RJW = Resync Jump Width - 1 = 4 - 1 = 1 */

/* SMP = 0: use 1 bit per CAN sample */

/* CLKSRC=0 (unchanged): Fcanclk= Fxtal= 25 MHz*/

//CAN_A.CTRL1.R = 0x04E40004;

// CAN_A.CTRL1.B.PRESDIV = 4;

// CAN_A.CTRL1.B.PSEG2 = 4;

// CAN_A.CTRL1.B.PSEG1 = 4;

// CAN_A.CTRL1.B.RJW = 1;

// CAN_A.CTRL1.B.CLKSRC = 0;

// CAN_A.CTRL1.B.LPB = 0;

// CAN_A.CTRL1.B.SMP = 0;

// CAN_A.CTRL1.B.LOM = 0;

// CAN_A.CTRL1.B.PROPSEG = 4;

CAN_A.CTRL1.B.PRESDIV = 2;

CAN_A.CTRL1.B.PSEG2 = 1;

CAN_A.CTRL1.B.PSEG1 = 1;

CAN_A.CTRL1.B.RJW = 1;

CAN_A.CTRL1.B.CLKSRC = 0;

CAN_A.CTRL1.B.LPB = 0;

CAN_A.CTRL1.B.SMP = 0;

CAN_A.CTRL1.B.LOM = 0;

CAN_A.CTRL1.B.PROPSEG = 1;

// code to disable ECC reporting at all

CAN_A.CTRL2.B.ECRWRE = 1; // enable editing of MECR

CAN_A.MECR.B.ECRWRDIS = 0; // enable writes to MECR

CAN_A.MECR.R = 0x00000100; // disable ECC error ISR and disable ECC at all , keep normal operation

CAN_A.CTRL2.B.ECRWRE = 0; // lock the MECR again

 

/* Make first 32 message buffers inactive by writing their control fields

to "not active". They will be left inactive until we're ready for communication. */

for(i=0;i<64;i++)

{

CAN_A.MB[i].CS.R = 0;

}

/* set mask registers - all ID bits must match */

for(i=0;i<64;i++)

{

CAN_A.RXIMR[i].R = 0x1FFFFFFF;

}

/* Finally clear the HALT flag in MCR to enable the FlexCAN

* to synchronize with the CAN bus and allow

* participation in communication. */

CAN_A.MCR.B.HALT = 0;

/* wait until FlexCAN ready */

while(1 == CAN_A.MCR.B.FRZACK) {}

while(1 == CAN_A.MCR.B.NOTRDY) {}

}

could some one guide me I'm getting stuck here while(1 == CAN_A.MCR.B.FRZACK) {}.

Regards,

Vignesh

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NXP TechSupport
NXP TechSupport

please sent simple project you have which shows the issue, so we can test it on the EVB.

BR, Petr

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Contributor III

Hi,

   I may not be able to share my project but anyways i'll try to get a project created only with the CAN settings/initializations. May be

give me sometime for that. Meanwhile for the clock configurations I said

sysclock - 25 MHZ per clock 100MHZ is the configuration for the control register for CAN is correct

Could you please let me know that from the above code snippet of CANinitializations?

Regards,

Vignesh

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NXP TechSupport
NXP TechSupport

Hi,

the PE clock (25MHz) must be higher that FlexCAN module clock (FM_PER_CLK).

Your CAN bit timing seems to be incorrect. Possible option could be 

CANx_CTRL1 = 0x04590002;  // bitrate=500kbps, CPI clk=25 MHz; Prescaler= 5, PROPSEG=3, PSEG1=4, PSEG2=2, RJW=2, smp=80%

BR, Petr

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Contributor III

Hi,

 I

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Contributor III

Hi,

 I tried with above configuration also. I'm finding similar issue . I'm attaching a test project which has configuration that I set.

Please let me know what is the issue still if possible.

Regards,

Vignesh

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Contributor III

Hi,

   I tried to upload the zipped project I'm not able to. Pl guide me how to do so.

Regs,

Vignesh

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