hello , I have a project on Can Flash Boot Loader Routine. I have some wonders.
Because in my demo flash boot loader, some functions of FBL routine is replaced in the SRAM . I wonder that when the FBL is excuted from flash , the entire flash section can not be erased and programed.
If the flash loader routine is excuted from one section in the flash, Could the FBL routine erase the another section and program the app in that section ?
Thank you very much !
there's only one rule - you can't access partition which is being programmed or erased. The partitions are described in Table 5-4:
So, the code must be executed from another partition or from RAM memory. If interrupts are used, either disabled them or ensure that it will not access programmed partition during the flash operation.
Lukas, Thank you very much !
I have find two demo about MPC5748G of flash manipulation on your website, one is using SSD and another is not .
Could you please give some Instruction Document on the SSD ? And I also need the SSD source files, Could you provide for me ?
Hello , I have check the User's Manual of the SSD.
About the 3.3 Notes and Limitations.
On the 3, how to disable the D-cache ? I have check the SSD demo just disable the flash controller buffer, but not disable the D-cache.
Could you give me some advice?
see this file:
c:\Program Files (x86)\Freescale\Standard Software Driver v1.1.0\MPC57xx\Demos\Demo_code\common\DCache.c
Function "dcache_disable" disables the data cache. It writes L1CSR0 register:
Thank you very much!
Besides, If I don't use SSD, just manipulate the register to erase and program the flash. The Notes and Limitations 3 and 4 mentioned above are unnecessary ,right ?
No, it doesn't matter if you use SSD drivers or if you write the flash registers by your own code. The result is the same.
For example, let's say that that there are some data in flash, you read them by your SW, so they are cached in data cache memory. If you erase that block now (and it doesn't matter if you do that by SSD drivers or by own code), the cache is not informed about that, so there are still old data. There's no HW coherency unit. You need to either invalidate the cache manually or this area must be set as cache inhibited. Or disable the cache completely but this is usually not an option due to performance.