FS65 Reset and SW Reset on MPC5744P

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FS65 Reset and SW Reset on MPC5744P

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latheef
Contributor III

I have  the MC33FS6522NAE as the SBC connected to 5744P.  I need to disable the SBC WDG & FCCU in the boot and initialize  it in App.

1)  At POR in the boot , Check for the Valid App if present Move to the App. No SBC initialization in Boot and  when in App perform the SBC Initiazation with WDG and FCCU enabled.

2)  Once in App, if Flashing tool (UDS) sends jump to Boot msg (10 02 Reprogramming) , the App updates a stay_in_boot flag (in ram) and does SW Reset using below code

    MC_RGM.FRET.B.FRET = 0x010;

    MC_ME.MCTL.R = 0x00005AF0; /* writes the key */

    MC_ME.MCTL.R = 0x0000A50F; /* writes the inverted key */

3) Now after the SW reset(as mentioned in step2), I use below to know the reset reason in the boot. But how do I distinguish between the Jump to Boot request and SBC RstB assertion. Can I Check on MC_RGM_FBRE.BE_Soft_func  bit to introduce new enum MCU_SBC_RESET below?

if( MC_RGM.DES.B.F_EDR ) {
rv = MCU_POWER_ON_RESET;
} else if( MC_RGM.FES.B.F_SOFT_FUNC ) {
rv = MCU_SW_RESET;
} else if( MC_RGM.DES.B.F_POR || MC_RGM.FES.B.F_EXR ) {
rv = MCU_POWER_ON_RESET;
} else {
rv = MCU_RESET_UNDEFINED;
}

4) If  I get pass through above step3 and see the reason as MCU_SW_RESET(bcos of step2) proceed to check on the  stay_in_boot  flag if it is set then Change SBC WD Period to 0 to disable(will SBC allow me to disable the WDG)  and wait for the UDS on CAN for flashing.

5) Once done with App Flashing or Timeout (no request from tool), then I will request a rstb low pulse by setting the bit  Rstb_req in SF_OUTPUT_REQUEST to reset so that SBC is in INIT_FS mode and I can configure the SBC  when in App.

Is this normal way of configuring the SBC FS65 to work both with APP and Boot?

Also will the stay_in_boot retain the value in SBC RSTB assertion? It does retain for SW Reset mentioned in Step 2.

 

Thanks & Best Regards!

 

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Search for LPOFF keyword in the documentation for FS65. This is from AN5238:

lukaszadrapa_0-1664998883430.png

Regards,

Lukas

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cuongnguyenvan
NXP Employee
NXP Employee

Hello,

If you already initialized FS65 in the boot (already close the INIT_FS), you cannot re-configure the WDG, FCCU after that.
you can do it with both boot and app if you don't connect the RSTB from SBC to MCU. ( non-connect avoid resetting MCU immediately).
If the RSTB connects to MCU, we cannot do it. However, I suggest the scenario.
My case will ignore the DEBUG mode.

1. Boot will init everything Wdg_disable, FCCU, Reaction...

Then you release FSxB safety pin to move NORMAL_FS mode.

Next step, you switch to App. If you want to control wdg(enabling), you can re-config the wdg_window. This time you must refresh wdg with time-synchronous.

If you want to update the new APP, you can reset SBC by sending the reset command via SPI and you will control the boot check the Can message for updating.

2. Wdg window enable. You should set wdg window bigger but least than 256ms because SBC will reset if no wdg refresh in first 256ms.

You can release fsxb pin... and then switch the app. 
However, I think that don't use this user case. It's not safety.

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latheef
Contributor III

@cuongnguyenvan  Thanks for the reply!

I do have the RSTB from SBC connected to to MCU.

For the scenario1 :

You said:

Boot will init everything Wdg_disable, FCCU, Reaction...

-> I was disabling SBD WDG(by setting cnt as 0) and disabing FCCU because of below from the manual.

Now I wil enable it. 

latheef_0-1663946242489.png

 Then you release FSxB safety pin to move NORMAL_FS mode.

->  Did you mean NORMAL_WD  ? if so when we perform our first  WDG perform it will move to  NORMAL_WD. Not sure how the release of FSxB affect the mode, Am I missing something.

latheef_1-1663946741572.png

 

Next step, you switch to App. If you want to control wdg(enabling), you can re-config the wdg_window. This time you must refresh wdg with time-synchronous.

-> Only thing I change is the Wdg_Window cnt to 6ms in the App , and Just refresh WDG every 6ms. But then all my safety configuration requirement need  to be traced to boot code  as not implemented in App?

If you want to update the new APP, you can reset SBC by sending the reset command via SPI and you will control the boot check the Can message for updating.

-> If I use the  Rstb_req in SF_OUTPUT_REQUEST to reset to move from App to Boot then the stay_in_boot flag (in ram) is lost as mentioned by @lukaszadrapa . In that case I cant use stay_in_boot and then how do I distinguish between this RSTB Assertion with  the actual (WDG refresh fault or other FCCU) RSTB assertion.

Thanks @cuongnguyenvan  and  @lukaszadrapa  for your reply!

 

 

 

 

 

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cuongnguyenvan
NXP Employee
NXP Employee

Hi
latheef

NORMAL_FS is just a mode as I remember.
you can understand it below.

Init_FS------------------> AssertFSxB pin ----------------> Nornal_FS

From InitFS to Assert FSxB needs close initfs by first Wdg refreshing

From Assert FsxB to NormalFS need to clear all fault error counters and execute the release FSxb command by SPI.
As I know, No SBC or PMIC device allows to re-configure the failsafe setting.
You can enable the FCCU monitor from the boot.
However, other devices like VR5510, FS86, FS84 allow you go back Init FS and you can re-configure the Safety setting.
You can consider it.

Thanks
Cuong

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cuongnguyenvan
NXP Employee
NXP Employee

Hi

I have remembered a case and hope that it can help you.
In the App, You can enter SBC into the LPOFF mode and wake up - reconfigure the FS again.
Because the FS register will load the default value after wakeup from LPOFF mode (the main register does not need to reconfigure)
Unfortunately, the RSTB still raises a signal when SBC comes to LPOFF mode.

That's all I understand about the SBC device.

Regards

Cuong

 

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

- command "MC_RGM.FRET.B.FRET = 0x010;" has no meaining, FRET bit field is 4-bit wide only

- if you want to use RGM_DES and RGM_FES to find the source of last reset, you should clear the registers after each reset. Then you will easily find which was the last one. If you triggered functional reset by SW in Mode Entry, F_SOFT_FUNC in RGM_FES will be set, if the reset is triggered externally by SBC then F_EXR in RGM_FES will be set.

- FS65 won't allow you to disable the watchdog once the init phase is finished.

- RAM content is not lost on functional reset.However BIST (build in self test) destroys RAM content. It is by default enabled.
BIST is executed during reset on following resets:Power on Reset, Long external reset, Destructive reset.

Regards
Lukas

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latheef
Contributor III

@lukaszadrapa 

if(MC_RGM.FES.B.F_EXR) doesnt help me to differentiate between the SW_Reset and SBC ext Reset.
Could you please provide me the code to distinguish between POR, SW Reset and SBC Ext reset?
Until now we only had POR/SW Reset. But now when SBC reset is implemented, on the RSTB resets the mcu takes the path of SW Reset (not init sram and other stuff) and it end up in exception. I think SBC Reset should be initialized same as the POR to fix the exception.
Thanks!
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latheef
Contributor III

I am using the below code to clear the reset reason . Is it right

    MC_RGM.DES.R = 0;/* Clear */
    MC_RGM.FES.R = 0/* Clear */

After the SW reset from App, when it reaches boot I perform a RSTB_Req after check in stay-in-boot and setting the WD_Window to 512ms and when it comes back on RSTB I look for WD_Window 512ms  then disable the WD so that I can continue with flashing.

But after RSTB it gives exception on CAN Reception. I checked the reset reason and it shows as SW Reset . Is it because the Reset Reason is not cleared correctly?

Help is much appreciated!

 
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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

If you have configured external reset as long reset then the BIST will destroy the RAM content. So yes, you should treat external reset in the same way as POR reset – the RAM should be initialized and the previous content is lost. If you want to avoid this, configure external reset as short reset.

If you take a closer look at the description of RGM_DES and RGM_FES registers, you will see that the flags are cleared by writing ‘1’:

lukaszadrapa_0-1664457387208.png

So, it should be:

MC_RGM.DES.R = 0xFFFFFFFF;/* Clear */

MC_RGM.FES.R = 0xFFFFFFFF; /* Clear */

Regards,

Lukas

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latheef
Contributor III

@lukaszadrapa  I really appreciate your response.

I tried setting the RSTB_DURATION = 1 and confirmed it by reading the FSSM as shown below at 

Below is at POR

latheef_2-1664538454552.pnglatheef_3-1664538517611.png

Below after RSTB_Req = 1

latheef_4-1664538647091.png

 

But the RSTB pin on the scope still shows 15 ms instead of 1 ms for short reset. Please let me know if I need to do anything more for short reset?

latheef_0-1664538195605.png

 

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lukaszadrapa
NXP TechSupport
NXP TechSupport

I'm sorry, I should be more clear: short reset sequence can be configured by MC_RGM_FESS register:

lukaszadrapa_0-1664781148793.pnglukaszadrapa_1-1664781175161.pnglukaszadrapa_2-1664781197029.png

By default, the external reset is configured as long reset ('0'), so just set it to '1' for short reset sequence.

Regards,

Lukas

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latheef
Contributor III

I am very new to the powerpc architecture and your reply has been very helpful . Could you please answer me below question too?

@lukaszadrapa How do I power off the ECU from Software.

I checked both from MCU and SBC docs but couldn't find a way of doing it.

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Search for LPOFF keyword in the documentation for FS65. This is from AN5238:

lukaszadrapa_0-1664998883430.png

Regards,

Lukas

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