FCCU fast switching mode

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FCCU fast switching mode

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zqdc77
Contributor I

The MPC5777MRM say:

The signal polarity can be programmed by setting the PS field in the FCCU_CFG
register. For example, for PS = 0, EOUT[0] = 0 and EOUT[1] = 1 in FAULT state for bi
stable and for PS = 1, it is inverted. All the diagrams and tables are related to the default
configuration selection: switching mode (FCCU_CFG.SM = 0). In case of inverted
polarity (FCCU_CFG.PS = 1) all the values on the EOUT output pins are inverted.
Two modes can be programmed to define the EOUT protocol transitions in dual-rail or
time-switching mode:
• slow switching mode: no EOUT frequency violation during the FCCU state
transition (NORMAL to FAULT or viceversa and CONFIG to NORMAL). The
EOUT protocol transition occurs after a max delay equal to the duration of the semi
period of the EOUT frequency.
• fast switching mode: The EOUT protocol transition (NORMAL to FAULT or
viceversa and CONFIG to NORMAL) occurs immediately. A pulse with the
minimum duration corresponding to 16 MHz/1024 (IRCOSC clock) period can occur
in fast switching mode. It implies a frequency violation of the EOUT protocol

 

"A pulse with the
minimum duration corresponding to 16 MHz/1024 (IRCOSC clock) period can occur
in fast switching mode."  I can't understand it. what is mean? how to impact the FCCU report fault through the   EOUT? 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

The pulse is show in reference manual for better understanding:

petervlna_0-1726220280366.png

petervlna_1-1726220460804.png

Hope it helps,

If not I can ask application engineer for explanation.

Best regards,

Peter

 

 

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

A pulse with the minimum duration corresponding to 16 MHz/1024 (IRCOSC clock) period can occur in fast switching mode."

It means due to clock synchronization you can see a "false"pulse on your FCCU out pins. Due to change of protocol.

But you wont be doing protocol changes in application run, but in configuration phase.

A pulse with the minimum duration corresponding to 16 MHz/1024 (IRCOSC clock) period can occur in fast switching mode.

I expect this just to ensure any external device monitoring FCCU EOUT wont see this glitch as fault.

Best regards,
Peter

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zqdc77
Contributor I

hi, petervlna

thank you ! 

I have some confusions

A pulse with the minimum duration corresponding to 16 MHz/1024 (IRCOSC clock) period can occur in fast switching mode.

1: if the FCCU receive the fault (example sram ecc err report ) in application run it will change NORMAL to FAULT, this pulse maybe occur.so it is not only in configuration phase. it maybe occur  in application run

2: If this is a 'false' pulse, and the external device monitoring FCCU EOUT does not consider this glitch as a fault, then using the term "minimum" is not appropriate, because in this case, the FCCU EOUT device would not know how long the glitch might last.

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