I want to enable Hardware interrupt on pressing of a switch. If I press the switch GPIO92(MPC5744P) the ISR should be executed. I am new to this controller If anyone Could point out where I am wrong, I would be very thankfull.
Thanks in advance!!!!
I tried the following:
/*INIT*/
SIUL2.MSCR[45].R = 0x32000000; //PA[0] GPIO - LED1
SIUL2.GPDO[45].R = 1;
// SIUL2.MSCR[92].B.IBE = 1;
//SIUL2.GPDI[92].B.PDI = 1;
/*SW1 init*/
SIUL2.MSCR[92].R = 0x00090000; //IBE, Pull-down
SIUL2.DIRER0.R = 0x00000002; //enable interrupt
SIUL2.IREER0.R = 0x00000002; //rising edge event enabled
SIUL2.IFER0.R = 0x00000002; //enable interrupt filter
SIUL2.IMCR[203].R = 0x00000001;
/*ACTION*/
SIUL2.GPDO[45].R = ~SIUL2.GPDO[45].R;
/*MAIN*/
INTC_0.PSR[243].R = 0x8005; //Set priority for SW1 interrupt
/*HANDLER*/
SW1Handler:
//# PROLOGUE
e_stwu r1, -0x50 (r1) //# Create stack frame and store back chain
se_stw r3, 0x28 (r1) //# Store a working register
//# Note: use se_ form for r0-7, r24-41 with positive offset
mfsrr0 r3 //# Store SRR0:1 (must be done before enabling EE)
se_stw r3, 0x0C (r1)
mfsrr1 r3
se_stw r3, 0x10 (r1)
wrteei 1 //# Set MSR[EE]=1
e_stw r12, 0x4C (r1) //# Store rest of gprs
e_stw r11, 0x48 (r1)
e_stw r10, 0x44 (r1)
e_stw r9, 0x40 (r1)
e_stw r8, 0x3C (r1)
se_stw r7, 0x38 (r1)
se_stw r6, 0x34 (r1)
se_stw r5, 0x30 (r1)
se_stw r4, 0x2C (r1)
se_stw r0, 0x24 (r1)
mfcr r3 //# Store CR
se_stw r3, 0x20 (r1)
mfxer r3 //# Store XER
se_stw r3, 0x1C (r1)
se_mfctr r3 //# Store CTR
se_stw r3, 0x18 (r1)
se_mflr r4 //# Store LR
se_stw r4, 0x14 (r1)
e_bl SW1_ISR //# Branch to ISR, but return here
//# EPILOGUE
se_lwz r3, 0x14 (r1) //# Restore LR
se_mtlr r3
se_lwz r3, 0x18 (r1) //# Restore CTR
se_mtctr r3
se_lwz r3, 0x1C (r1) //# Restore XER
mtxer r3
se_lwz r3, 0x20 (r1) //# Restore CR
mtcrf 0xff, r3
se_lwz r0, 0x24 (r1) //# Restore other gprs except working registers
se_lwz r5, 0x30 (r1)
se_lwz r6, 0x34 (r1)
se_lwz r7, 0x38 (r1)
e_lwz r8, 0x3C (r1)
e_lwz r9, 0x40 (r1)
e_lwz r10, 0x44 (r1)
e_lwz r11, 0x48 (r1)
e_lwz r12, 0x4C (r1)
mbar 0 //# Ensure store to clear interrupt flag bit completed
e_lis r3, INTC_EOIR@ha //# Load upper half of EIOR address to r3
se_li r4, 0
wrteei 0 //# Disable interrupts for rest of handler
e_stw r4, INTC_EOIR@l(r3) //# Write 0 to proc'r 0 INTC_EIOR
se_lwz r3, 0x0C (r1) //# Restore SRR0
mtsrr0 r3
se_lwz r3, 0x10 (r1) //# Restore SRR1
mtsrr1 r3
se_lwz r4, 0x2C (r1) //# Restore working registers
se_lwz r3, 0x28 (r1)
e_add16i r1, r1, 0x50 //# Delete stack frame
se_rfi //# End of Interrupt
