Exception&Interrupt of S32R274

[Durant-Harden-Irving]

Hello,

Sorry to trouble you. 

My question is:

1. How to config the IVPR in Z7 cores?   

I have config the IVPR in Z4 core(mtIVPR address), and works well.  Can I use the same method to config the IVPR in Z7 cores(mtIVPR address, just the address is diffrent)

2. When a exception occur(eg. miss-align ) in Z7 core,  exception handler function will not be called(Just notify the exception handler in Z7 core), am I right?

3. When I call the interrupt enable (asm(" wrteei 1")) in Z7 core， does it affect the Z4 core？

4. Can you tell me how to get the core ID in greenHills envirenment?  I use "__MFSPR(286)" , but the return value is wrong.

Is there the documents describing the above knowledges?

Thanks very much?

[Durant-Harden-Irving]

Thanks!

2) When a exception occur(eg. miss-align ) in Z7a core, does it affect the Z4 core? 

[davidtosenovjan · Accepted solution]

I see. No, it doesn't.

[Durant-Harden-Irving]

Get it, thank you!

[davidtosenovjan]

Hi,

1) For instance following way:

    #IVPR = address base used with IVOR's

    e_lis r5, __IVPR@h  

    e_or2i r5, __IVPR@l

    mtIVPR r5

2) I am afraid I don’t understand this question at all. Could you clarify it?

3) No, the instruction affects the core executing this instruction.

[Durant-Harden-Irving]

Hello，

The question 4 is solved. Now I can get the core ID.

Please know.