Effect of MSR[PR] Bit on BDM and JTAG Debugging in PowerPC in MCP561

[imsujith3]

I am working with PowerPC architecture and trying to understand the impact of the MSR[PR] (Privilege) bit on debugging interfaces.

When MSR[PR] is set, does it completely disable Background Debug Mode (BDM) and JTAG development support, or does it only restrict certain debugging functionalities?

Additionally, is there any way to override this restriction for debugging purposes, such as through special debug modes or external tools?

Any insights or references to relevant documentation would be greatly appreciated.

I attached user manual for your Reference

[lukaszadrapa]

Hi @imsujith3 

PowerPC processors have two levels of privilege: supervisor mode of operation (typically used by the operating system) and user mode of operation (used by the application software).

It does not disable BDM/JTAG access at all. If debug mode is entered, privileged mode is entered automatically. From MPC561 RM:

"Upon entering debug mode, the processor gets into the privileged state (MSR[PR] = 0). This
allows execution of any instruction, and access to any storage location."

Regards,

Lukas

PS. Notice that MPC561 is in Not Recommended For New Designs status, so we can provide only very limited support.

[imsujith3]

Hi, Do you have any idea for disabling BDM/JTAG access..

[lukaszadrapa]

In general, MPC5xx devices have censorship feature which restricts access to internal flash. However, MPC561 has no internal flash, so it does not apply here. There's no such feature on MPC561.