Hi @johndiener,
The code is taken from the fs_etpu2_init function of AN4907. Thanks for your help.
Here is the full code for who read this topic and needs to further understanding.
uint32_t fs_etpu2_init(
struct etpu_config_t p_etpu_config,
uint32_t engine_mem_size)
{
/* 1. Initialize Watchdog Timer. */
/* Engine A Watchdog */
eTPU->WDTR_A.R = 0; /* disable first before a new mode is configured */
eTPU->WDTR_A.R = p_etpu_config.wdtr_a;
/* Engine B Watchdog */
/* Not all parts have a second eTPU engine, if don't these writes are ignored. */
eTPU->WDTR_B.R = 0; /* disable first before a new mode is configured */
eTPU->WDTR_B.R = p_etpu_config.wdtr_b;
/* 2. Allocate engine-relative data memory space for each engine. */
if(engine_mem_size > 0)
{
/* Engine A */
if(eTPU->ECR_A.B.MDIS == 0)
{
fs_free_param = (uint32_t*)((((uint32_t)fs_free_param+511)>>9)<<9); /* round up to 512s */
eTPU->ECR_A.B.ERBA = ((uint32_t)fs_free_param) >> 9;
fs_memset32(fs_free_param, 0, engine_mem_size);
fs_free_param = (uint32_t*)((uint32_t)fs_free_param + engine_mem_size);
}
/* Engine B */
if(eTPU->ECR_B.B.MDIS == 0)
{
fs_free_param = (uint32_t*)((((uint32_t)fs_free_param+511)>>9)<<9); /* round up to 512s */
eTPU->ECR_B.B.ERBA = ((uint32_t)fs_free_param) >> 9;
fs_memset32(fs_free_param, 0, engine_mem_size);
fs_free_param = (uint32_t*)((uint32_t)fs_free_param + engine_mem_size);
}
}
fs_free_param = (uint32_t*)((((uint32_t)fs_free_param + 7) >> 3) << 3); /* round up to 8s */
if ((uint32_t)fs_free_param > fs_etpu_data_ram_end)
return(FS_ETPU_ERROR_MALLOC);
else
return(0);
}
Best Regards,
Mert.