ETPU Phase A compliment channel not working

[amey_murkute]

Hello All,

      I am implementing Space vector modulation technique . I am using MPC5777C controller & trying to generate 3 phase signal that is 6 pwm's out of etpu function. I read that we need to provide the duty cycle to only compliment channels & etpu take care of other non-compliment channels. So I am trying to generate

A1_BOT --  Compliment channel- ETPUA0

A1_TOP

B1_BOT -- Compliment channel- ETPUA2

B1_TOP

C1_BOT -- Compliment channel- ETPUA4

C1_TOP

So after compiling code I am successfully got the PWM out of 2 phase channels that is B1_BOT & TOP, C1_BOT & TOP. But A1_BOT pwm pulse is not getting out. So what is the reason behind it. I am getting A1_TOP pwm of this channel but not getting A1_BOT. So why only a single leg getting problem. The following is pwm_init function which I am using.

err_code = fs_etpu_pwmmac_init_3ph (
PWM_master_channel, /* master_channel */
FS_ETPU_PRIORITY_HIGH, /* priority */

PWM_phaseA_channel, /* phaseA_channel */
FS_ETPU_PWMMAC_DUTY_POS, /* phaseA_negate_duty */
PWM_phaseB_channel, /* phaseB_channel */
FS_ETPU_PWMMAC_DUTY_POS, /* phaseB_negate_duty */
PWM_phaseC_channel, /* phaseC_channel */
FS_ETPU_PWMMAC_DUTY_POS, /* phaseC_negate_duty */

FS_ETPU_PWMMAC_MOD_SVM_STD, /* SVM STD modulation */
&fs_etpu_pwmmac_sin3h_lut[0], /* p_table */

FS_ETPU_PWMMAC_NORMAL, /* update */
FS_ETPU_PWMMAC_CENTER_ALIGNED, /* alignment */
FS_ETPU_PWMMAC_FULL_RANGE_COMPL_PAIRS, /* phases_type */
FS_ETPU_PWMMAC_NO_SWAP, /* swap */
FS_ETPU_PWMMAC_PIN_HIGH, /* base_ch_disable_pin_state */
FS_ETPU_PWMMAC_PIN_LOW, /* compl_ch_disable_pin_state */

10000, /* start_offset */
etpu_a_tcr1_freq/PWM_Switching_Freq, /* period (frequency) */
etpu_a_tcr1_freq/PWM_Switching_Freq/2, /* update_time */
etpu_a_tcr1_freq/1000*PWM_dead_time_ns/1000000, /* dead_time */
etpu_a_tcr1_freq/1000*PWM_dead_time_ns/1000000); /* min_pw */

/*******************************************************************************
* Enable generation of PWM signals
*******************************************************************************/
hsrr = fs_etpu_pwmmac_enable_3ph(PWM_master_channel,
FS_ETPU_PWMMAC_PIN_LOW ,
FS_ETPU_PWMMAC_PIN_LOW );

return (err_code);

for SVM implemenation using following etpu function

fs_etpu_pwmmac_update_svm(PWM_master_channel, (Alpha_Angle * 4194304), (Beta_Angle * 4194304)); 

Thanks.

[amey_murkute]

Hello All,

         As discussed above, also I have generated the 10Khz pwm through the following function.

fs_etpu_pwm_init(resolver_channel,FS_ETPU_PRIORITY_MIDDLE,10000,5000,FS_ETPU_PWM_ACTIVEHIGH,FS_ETPU_TCR1,etpu_a_tcr1_freq);

So is there any problem using two etpu function in one project?. Because it seems that when I disable above 10Khz pwm etpu function then my 3 phase pwm works fine.

Thanks & regards,

Amey

[davidtosenovjan]

Hi, in principle it is not an issue to have more eTPU functions in one project, it is the way how eTPU is being used.

What can be potentially the issue is the worst case latency for a channel (longest period of time that can elapse between the execution of any two function threads on that channel) that is affected by activity on the other channels.

See section 4.3 in the eTPU function set descriptive document:

https://www.nxp.com/docs/en/application-note/AN2968.pdf 

[amey_murkute]

Hi David,

  Thanx for the inputs. When I am using the following function then it works fine.

fs_etpu_pwmmac_init_3ph();     // Used for 3 phase sine wave generation

fs_etpu_pwmmac_init_1ph();     //  Used for 10KHz pwm generation with constant 50%duty cycle.

& when I use the following function I get the 3 phase leg-A bottom pulse missing.

fs_etpu_pwmmac_init_3ph();     // Used for 3 phase sine wave generation

fs_etpu_pwm_init(resolver_channel,FS_ETPU_PRIORITY_MIDDLE,10000,5000,FS_ETPU_PWM_ACTIVEHIGH,FS_ETPU_TCR1,etpu_a_tcr1_freq);    //  Used for 10KHz pwm generation with constant 50%duty cycle.

So I think there is problem while executing the RAM code of etpu, because in first case the RAM code for both function is same but in the next there are two seperate etpu RAM Code.

So is my understanding is correct? 

Thanks.

Amey