I have read the Error Correcting Codes Implemented on MPC5744P (Rev. 0, Draft B,12/2017) which was written by you earlier. I have some doubts about ECC & EDC. Could you answer my questions?
1. How to generate the ECC checkbits
There is no detail introduction about the implement of ECC algorithm in RM or Error Correcting Codes Implemented on MPC5744P. I mean how to generate the ECC check bits was not clarified. Is ECC algorithm similar to Parity check?
2. The difference between e2eECC and ECC.
As described in RM Table 3-1. ECC comparison of data write then read sequence, the e2eECC checkbits which is provided by master include coverage of address and data information, while the ECC check-bits which is provided by slave memory include data information only?
3. The function of EDC
“in most cases it is additional EDC protection (supervision), checksum being added and subsequently removed from/to data, address, attribute or other signals, according the specific needs of protected transfer or memory module. It is further protection capable to find ECC malfunction”.
Is EDC an algorithm for check the ECC correction logic? But how to check? By decoding ECC?
By the way, does SRAM has EDC?
4. ECC manipulation / ECC re-coded
Why is ECC re-coded due to removing of address portion from transferred packet address, data, e2eECC. I mean why does the address portion need to remove from the full ECC?
And how? By EDC?
I am looking for forward to hear from you.
Hi, I would like to note, that the document is really preliminary and it is possible that some description will be changed. Maybe the diagram is too oversimplified, on the other hand I don’t want to have it too complex, only to sketch some basic ideas.
1) The basic principle is based on certain XOR operations with protected data patterns. It is much complex operation then the parity. If you need more detail try to find certain scientific articles about Hamming and HSIAO SEC-DEC codes.
In certain our manuals, you can find some description, for instance here (32.5.1 Hsiao ECC algorithm):
2) Yes, it is so. But the main point is that e2eECC protects the whole access path, not only memory content. It is quite well described in reference manual, section 3.4:
3) The EDC after ECC detects a failure affecting the ECC logic. Unfortunately, deeper technical details are confidential proprietary. It just something what is being done on the side of flash controller to guarantee correct and protected access to the flash and in case of malfunction it can lead in NCF34/35.
4) It is due to physical storage of data in the flash memory. An address points to certain place whilst the data and ECC are supposed to be stored in the physical flash memory.