I have confusion on how to configure the data and address lines in EBI of MPC5777C controller.
I want to use Muxed-32 bit mode (with two 1Mx16 MRAM chips (20 address lines) and two 64Mx16 NOR Flash chips) with chip selects 0 and 1 for MRAM and NOR flash respectively.
As shown in the table above, Address [9:15] are dedicated address pins and functionality will always be address irrespective of mode settings.
D_ADD_DAT[0:15] pins are multiplexed for Add#ress[0:15] and Data[0:15].
First of all, in pin-out of the controller, this name is not mentioned on these pins and it is mentioned as D_DAT[0:15].
1. Are these pins really multiplexed? or only function is data?
2. If they are multiplexed with Address[0:15], then Address[9:15] is getting duplicated at two places.
Will it be generated at two set of pins?
3. Address[9:15] can also be configured as GPIOs.
If I do so, will address duplication affect the function of my GPIOs, in case answer to question 2 is yes?
how pins D_OE, D_WE0, D_WE1, D_WE2, D_WE3, D_RD_WR are supposed to be used for different chip selects?
1) Yes, it is marked confused way but these pins can works as D_ADD_DAT[0:15] in multiplexed mode. I will suggest documentation improvement.
2) These are duplicated but D_ADD[9:15] contains only address thus they may not be buffered.
3) Yes, you can use these pins as GPIO if you don’t need it for EBI purpose.
4) D_OE, D_WE0, D_WE1, D_WE2, D_WE3, D_RD_WR will be shared for all devices connected (if all used, flash memories typically don’t need all WE lines). Only CS lines distinguish between connected device.
I have one more question on this:
In 32-bit muxed mode, will ADD[9:15] be dedicated address lines? Will the address be valid throughout the write or read cycle?
I am basically latching only ADD_DAT[16:31] signals and connecting ADD[9:15] directly to memory to avoid using another latch for ADD_DAT[0:15] signals.
Will this work?