Doubt about MASK in MPC5748G Reference Manual

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Doubt about MASK in MPC5748G Reference Manual

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antleite2001
Contributor I

From Project BlinkingLed

https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-Create-a-Blinking-LED-Project-MP...

function

void pitCh0Handler(void)
{

/* Clear PIT channel 0 interrupt flag */

PIT_DRV_ClearStatusFlags(INST_PIT1, 0U);

/* Toggle LED (GPIO 0 connected to user LED 2) */

SIUL2->GPDO[0] ^= SIUL2_GPDO_PDO_4n_MASK; // DEV-KIT

/* SIUL2->GPDO[99/4] ^=SIUL2_GPDO_PDO_4n3_MASK;*/// Motherboard
}

From the define below

#define SIUL2_GPDO_PDO_4n_MASK 0x1000000u

0x1000000u = 0001.0000.0000.0000.0000.0000.0000b (bit 24 is on)

it seems that pin 24 is set to force the xor operation over the register SIUL2->GPDO[0]

BUT

from Document Number: MPC5748GRM Rev. 7.1, 01/2019, page 394 section  15.2.13 SIUL2 GPIO Pad Data Output Register (SIUL2_GPDOn)

this bit should be the 7th

Then the mask should be

0x80 = 1000.0000b

Am I missing something or the datasheet is enumerating the bits in opposite direction (31 should be 0 and bit 0 should be 31)?

Thanks in Advance

Antonio Leite

 

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antleite2001
Contributor I

Thanks

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Antonio,

"or the datasheet is enumerating the bits in opposite direction" - yes, this is the reason.

Regards,

Lukas

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