Hello,
While playing with the MPC5554 cache configuration, I am measuring execution times when running some code with several cache configurations. At some point, I tried to deactivate the cache using two different approaches (my code snippets use Green Hills asm syntax):
i) Using the last bit of L1CSR0
__asmleaf void turn_cache_off() {
mfspr r3, l1csr0
clrrwi r3, r3, 1
msync
isync
mtspr l1csr0, r3
isync
}
ii) Flushing/invalidating the entire cache, then disabling line replacement in all its ways
ii-1) Flush+invalidate
__asmleaf void flush_inv_cache_line(uint32_t flushed_way, uint32_t flushed_set) {
%reg flushed_way %reg flushed_set
mfspr r3, l1finv0
insrwi r3, flushed_way, 5, 3
insrwi r3, flushed_set, 7, 20
li r4, 2
rlwimi r3, r4, 0, 30, 31
msync
mtspr l1finv0, r3
}
void flush_inv_cache(void) {
uint32_t i;
uint32_t j;
for (i = 0u; i < 8u; i++)
{
for (j = 0u; j < 128u; j++)
{
flush_inv_cache_line(i, j);
}
}
}
ii-2) Disabling line replacement
__asmleaf void turn_icache_off() {
mfspr r3, l1csr0
li r4, 15
insrwi r3, r4, 4, 0
li r4, 1
insrwi r3, r4, 1, 8
msync
isync
mtspr l1csr0, r3
isync
}
__asmleaf void turn_dcache_off() {
mfspr r3, l1csr0
li r4, 15
insrwi r3, r4, 4, 4
li r4, 1
insrwi r3, r4, 1, 9
msync
isync
mtspr l1csr0, r3
isync
}
It seems that my code runs faster with the second approach, which gives me the impression that somehow there is still cache activity somewhere. Do you know what is missing for me to have the same timing behavior in both cases?
Best regards,
Ricardo
