The goal is to update the software program into the flash of MPC5554 if requested by operator before launch the program alreay installed at address 0x20000 of internal flash.
At the start-up into my main() procedure (0x0000 of internal flash) I have to acces to as specific size of memory space ,connected to FPGA by EBI bus, by the following routine:
#define REG_READ16(addr) (*(volatile uint16_t*)(addr))
The problem is that when I try to access at this specific address the cache added also next 8 address data request
I disable the cache completely by the following instruction (disable all cache)
asm("mfspr r3, l1csr0");
asm("clrrwi r3, r3, 1");
asm("msync ");
asm("isync ");
asm("mtspr l1csr0, r3");
asm("isync ");
the read access is OK ........ but I have problem with procedure that init internal flash device:
returnCode = pFlashInit( &ssdConfig );
not works
In the main application (that use Integrity) by BSP I set this size of memory as:
#define FPGA_REG_BEGIN 0x3FD00000
#define FPGA_REG_END 0x3FD3FFFF
PhysicalRange BSP_PhysicalMemoryRanges[] = {
/* Attributes, PhysicalSpcaeNumber, First, Last, Type, name */
/* Same as "Basic memory regions" in ppc5554.h */
{ MEMORY_RWE | MEMORY_VOLATILE | MEMORY_IOCOHERENT, 0, FPGA_REG_BEGIN, FPGA_REG_END, };
My question: Is possibile to disable not all cache but only a for a specific address also into my main procedure ?
Could you suggest me an idea ?
Thanks in advanced
Hi, you may configure multiple address ranges by MMU TLB entries and use cache-inhibited attribute for areas where access in not supposed to be cached.
Following tool could be useful:
https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/MMU-Assist-Register-CONFIGURATOR/ta-p/1110436
Thanks David
I set the TLB as below , but I see that the cache is not disable yet.
; Modify Entry 6 to specify 0x3fd00000-0x3fd3ffff for FPGA registers
lis r12, %hi(0x10060000) ;
mtspr mas0, r12 ;
lis r12, %hiadj(0xc0000400) ;
addi r12,r12,%lo(0xc0000400) ;
mtspr mas1, r12 ;
lis r12, %hiadj(0x3fd0001e) ;
addi r12,r12,%lo(0x3fd0001e) ;
mtspr mas2, r12 ;
lis r12, %hiadj(0x3fd00005) ;
addi r12,r12,%lo(0x3fd00005) ;
mtspr mas3, r12 ;
tlbwe ; Set TLB entry
tlbsync
Do you have any other suggestion ?
Thanks in advanced
Are you using write-through or copy-back mode?
write-through
How can set the VOLATILE mode ?
Thanks
i am sorry, I don't understand context.
Sorry for mistake...
As explained before I try to read by the simple instruction (see below) the data into the FPGA by EBI bus.
#define REG_READ32(addr) (*((volatile uint32_t*)(addr)))
#define FPGA_RAM_TEST_REG 0x3fd23fe0
int main(int argc, char *argv[])
{
uint16_t value = 0;
value = REG_READ32(FPGA_RAM_TEST_REG);
}
I initialize the EBI bus as below, but when I try to read a data at the address (0x3FD23FE0), I can't see the chip select CSO in the oscilloscope. CSO not move. In the post before I talk about the cache (disable/enable), but I'm wrong because the access to memory it's coming from the emulator memory window left open for mistake.
Could you check if are there some error in the setting ?
Thanks in advanced
Setting-1:
; Modify Entry 6 to specify 0x3fd00000-0x3fd3ffff for FPGA registers
lis r12, %hi(0x10060000)
mtspr mas0, r12
lis r12, %hiadj(0xc0000400)
addi r12,r12,%lo(0xc0000400)
mtspr mas1, r12
lis r12, %hiadj(0x3fd0001e)
addi r12,r12,%lo(0x3fd0001e)
mtspr mas2, r12
lis r12, %hiadj(0x3fd00005) ; Start of FPGA, physical address
addi r12,r12,%lo(0x3fd00005) ; and permission bits SW, SR
mtspr mas3, r12 ; Set MMU Assist Register 3
tlbwe
; Invalidate TLB entries 7..31
li r12, 0x00000000 ; Set to zero
mtspr mas1, r12
mtspr mas2, r12
mtspr mas3, r12
li r11, 7
lis r12, %hi(0x01070000) ; Entry Select (ESEL) = 7, TLB Select (TLBSEL) = 1
settlb: mtspr mas0, r1
tlbwe
addis r12,r12,%hi(0x00010000)
addi r11,r11,1
cmplwi r11, 32
blt settlb ;
tlbsync
Setting-2:
;Configure I/O pins for external address bus
li r12, 0x0440
lis r11, %hi(0xc3f90000)
; Set Pad Configuration Registers 4..27 as ADDR[8..31]
; Set PA = 1 (primary function)
; Set DSC = 0b01 = 20pF drive strength
sth r12, 0x48(r11) ; 0xc3f90048 = 0x0440
sth r12, 0x4a(r11) ; 0xc3f9004a = 0x0440
sth r12, 0x4c(r11) ; 0xc3f9004c = 0x0440
sth r12, 0x4e(r11) ; 0xc3f9004e = 0x0440
sth r12, 0x50(r11) ; 0xc3f90050 = 0x0440
sth r12, 0x52(r11) ; 0xc3f90052 = 0x0440
sth r12, 0x54(r11) ; 0xc3f90054 = 0x0440
sth r12, 0x56(r11) ; 0xc3f90056 = 0x0440
sth r12, 0x58(r11) ; 0xc3f90058 = 0x0440
sth r12, 0x5a(r11) ; 0xc3f9005a = 0x0440
sth r12, 0x5c(r11) ; 0xc3f9005c = 0x0440
sth r12, 0x5e(r11) ; 0xc3f9005e = 0x0440
sth r12, 0x60(r11) ; 0xc3f90060 = 0x0440
sth r12, 0x62(r11) ; 0xc3f90062 = 0x0440
sth r12, 0x64(r11) ; 0xc3f90064 = 0x0440
sth r12, 0x66(r11) ; 0xc3f90066 = 0x0440
sth r12, 0x68(r11) ; 0xc3f90068 = 0x0440
sth r12, 0x6a(r11) ; 0xc3f9006a = 0x0440
sth r12, 0x6c(r11) ; 0xc3f9006c = 0x0440
sth r12, 0x6e(r11) ; 0xc3f9006e = 0x0440
sth r12, 0x70(r11) ; 0xc3f90070 = 0x0440
sth r12, 0x72(r11) ; 0xc3f90072 = 0x0440
sth r12, 0x74(r11) ; 0xc3f90074 = 0x0440
sth r12, 0x76(r11) ; 0xc3f90076 = 0x0440
; Set Pad Configuration Registers 28..43 as Data[0..15]
sth r12, 0x78(r11) ; 0xc3f90078 = 0x0440
sth r12, 0x7a(r11) ; 0xc3f9007a = 0x0440
sth r12, 0x7c(r11) ; 0xc3f9007c = 0x0440
sth r12, 0x7e(r11) ; 0xc3f9007e = 0x0440
sth r12, 0x80(r11) ; 0xc3f90080 = 0x0440
sth r12, 0x82(r11) ; 0xc3f90082 = 0x0440
sth r12, 0x84(r11) ; 0xc3f90084 = 0x0440
sth r12, 0x86(r11) ; 0xc3f90086 = 0x0440
sth r12, 0x88(r11) ; 0xc3f90088 = 0x0440
sth r12, 0x8a(r11) ; 0xc3f9008a = 0x0440
sth r12, 0x8c(r11) ; 0xc3f9008c = 0x0440
sth r12, 0x8e(r11) ; 0xc3f9008e = 0x0440
sth r12, 0x90(r11) ; 0xc3f90090 = 0x0440
sth r12, 0x92(r11) ; 0xc3f90092 = 0x0440
sth r12, 0x94(r11) ; 0xc3f90094 = 0x0440
sth r12, 0x96(r11) ; 0xc3f90096 = 0x0440
; Set Pad Configuration Registers 44..59 as Data[16..31]
sth r12, 0x98(r11) ; 0xc3f90098 = 0x0440
sth r12, 0x9a(r11) ; 0xc3f9009a = 0x0440
sth r12, 0x9c(r11) ; 0xc3f9009c = 0x0440
sth r12, 0x9e(r11) ; 0xc3f9009e = 0x0440
sth r12, 0xa0(r11) ; 0xc3f900a0 = 0x0440
sth r12, 0xa2(r11) ; 0xc3f900a2 = 0x0440
sth r12, 0xa4(r11) ; 0xc3f900a4 = 0x0440
sth r12, 0xa6(r11) ; 0xc3f900a6 = 0x0440
sth r12, 0xa8(r11) ; 0xc3f900a8 = 0x0440
sth r12, 0xaa(r11) ; 0xc3f900aa = 0x0440
sth r12, 0xac(r11) ; 0xc3f900ac = 0x0440
sth r12, 0xae(r11) ; 0xc3f900ae = 0x0440
sth r12, 0xb0(r11) ; 0xc3f900b0 = 0x0440
sth r12, 0xb2(r11) ; 0xc3f900b2 = 0x0440
sth r12, 0xb4(r11) ; 0xc3f900b4 = 0x0440
sth r12, 0xb6(r11) ; 0xc3f900b6 = 0x0440
; Set Pad Configuration Register 62 as RD/WR
sth r12, 0xbc(r11) ; 0xc3f900bc = 0x0440
; Set Pad Configuration Register 63 as /BDIP
sth r12, 0xbe(r11) ; 0xc3f900be = 0x0440
; Set PA = 1 (primary function)
; Set DSC = 0b01 = 20pF drive strength
; Set WPE and WPS
li r12, 0x0443
; Set Pad Configuration Registers64..67 as WE[0..3]
sth r12, 0xc0(r11) ; 0xc3f900c0 = 0x0443
sth r12, 0xc2(r11) ; 0xc3f900c2 = 0x0443
sth r12, 0xc4(r11) ; 0xc3f900c4 = 0x0443
sth r12, 0xc6(r11) ; 0xc3f900c6 = 0x0443
; Set Pad Configuration Register 68 as OE
sth r12, 0xc8(r11) ; 0xc3f900c8 = 0x0443
; Set Pad Configuration Register 69 as TS
sth r12, 0xca(r11) ; 0xc3f900ca = 0x0443
; Set Pad Configuration Registers 0..3 as /CS[0..3]
sth r12, 0x40(r11) ; 0xc3f90040 = 0x0443
sth r12, 0x42(r11) ; 0xc3f90042 = 0x0443
sth r12, 0x44(r11) ; 0xc3f90044 = 0x0443
sth r12, 0x46(r11) ; 0xc3f90046 = 0x0443
Setting-3:
; Set External Bus Interface (EBI)
; CS0 selects FPGA registers at 0x3fd00000, size 0x40000
lis r12, %hiadj(0x3fd00043) ;
addi r12,r12,%lo(0x3fd00043) ;
stw r12, 0x4010(r11) ;0xc3f84010 = (0xc3f80000+(0x43 or 0x843))
; Write EBI Option Register Bank 0 (EBI_OR0)
; 0xfffc0000 = Address Mask (AM)
; 0xf0 = Cycle Length (SCY) = 0xf
lis r12, %hiadj(0xfffc00f0)
addi r12,r12,%lo(0xfffc00f0)
stw r12, 0x4014(r11)
A principle could be correct (if i understand what you actually want to achieve). I haven't checked values.
Note to tlbwe instruction - in this sequence isync is required after and msync before
I solve by set the "VALID" bit of mas1 register as "This TLB entry is invalid"
instead of "This TLB entry is invalid"
Could you give me an explanation ? .......... to understand my error
Thanks
I haven't understand your description as it does not make sense.
VALID bit needs to be set to make the entry valid (i.e. active), otherwise it is invalid (inactive).