DEVKIT Evaluation Board for MPC5748G, Enable 40 MHz Crystal

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DEVKIT Evaluation Board for MPC5748G, Enable 40 MHz Crystal

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manuelmoreno-eg
Contributor II

Hi,

Please, can anyone give me an example to enable a clock of 40 MHz for FlexRay peripheral using the external crystal (40 MHz) of the DEVKIT MPC5748G?

Thanks in advance,

Manuel

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petervlna
NXP Employee
NXP Employee

Hi,

I cannot post you example SW due to legal rights.

However I will post code snippet:

void Sys_Init(void)
{
    // Auxiliary Clock 5 Source Selection Control
    MC_CGM.AC5_SC.B.SELCTL = 1;        //Fast external crystal osc.(FXOSC=40MHz)
    MC_ME.DRUN_MC.B.PLLON = 1;        //Enable PLL for DRUN mode

    // FMPLL module configuration
    // Set PLL0 to 160MHz (40MHz XTAL)
    // VCO Frequency Range 600 - 1280 MHz
    // RFDPHI1 = 10, RFDPHI = 2, PREDIV = 4, MFD = 0x40h (64)
    PLLDIG.PLLDV.R = 0x50000000 |0x00010000 |0x00004000 |0x0040 ;

    // PLL Calibration Register 3
    PLLDIG.PLLCAL3.R = 0x09C3C000;    //Denominator of fractional loop division factor
   
    //Configure RunPeripheralConfiguration registers in ME_RUN_PC0
    MC_ME.RUN_PC[0].B.DRUN = 1;        //Enable DRUN mode for all peripherals using ME_RUN_PC[0]
    
    //Enable external oscilator
    MC_ME.DRUN_MC.B.FXOSCON = 1;

    // System Clock Divider Configuration
    // S160 -> 160MHz
    MC_CGM.SC_DC[0].B.DIV = 0;         //Divide 0 Division Value
    MC_CGM.SC_DC[0].B.DE  = 1;        //Enable system clock divider 0
    // S80 -> 80MHz
    MC_CGM.SC_DC[1].B.DIV = 1;         //System Clock Divide by 2
    MC_CGM.SC_DC[1].B.DE  = 1;        //Enable system clock divider 1
    // FS80 -> 80MHz
    // MC_CGM_SC_DC1[DIV] and MC_CGM_SC_DC5[DIV] must be equal at all times
    MC_CGM.SC_DC[5].R = MC_CGM.SC_DC[1].R;
    // S40 -> 40 MHz
    MC_CGM.SC_DC[2].B.DIV = 3;         //System Clock Divide by 4
    MC_CGM.SC_DC[2].B.DE  = 1;        //Enable system clock divider 2
    // F40 -> 40 MHz
    // MC_CGM.SC_DC[3]-> System Clock Divide by 4 & enabled divider 3 by default
    // F80 -> 80MHz
    //MC_CGM.SC_DC[4]->  System Clock Divide by 2 enabled divider 4 by default
    // F20 -> 20MHz
    //MC_CGM.SC_DC[6]->     System Clock Divide by 8 & enable divider 6 by default

    // CLKOUT_0 - Auxiliary Clock 6
    MC_CGM.AC6_DC0.B.DE = 1;        //Enable output clock divider
    MC_CGM.AC6_DC0.B.DIV = 0x13;    //Divide output clock by 20
    MC_CGM.AC6_SC.B.SELCTL = 0x2;     //PLL_CLKOUT1 - current source

    // LIN0 - Auxiliary Clock 7
    MC_CGM.AC7_SC.R = 0;        //LinFlex source clock is F40

    // SPI0 - Auxiliary Clock 8
    MC_CGM.AC8_SC.R = 0;        //SPI0 source clock is F40

    // FlexCAN0 - Auxiliary Clock 9
    MC_CGM.AC8_SC.R = 0;        //FlexCAN0 source clock is FS80
      
    // switch to PLL
    MC_ME.DRUN_MC.R  = 0x00130172;       //FLASH in normal mode, PLLON, FXOSC ON, Use PLL_PHI_0
    
    //Mode transition to apply the PLL0 setup and set Normal mode with PLL running
    MC_ME.MCTL.R = 0x30005AF0;              //DRUN Mode & Key
    MC_ME.MCTL.R = 0x3000A50F;              //DRUN Mode & Key

    while(!MC_ME.GS.B.S_PLLON);              //ME_GS Wait for PLL stabilization.
    while(MC_ME.GS.B.S_MTRANS);             //Waiting for end of transaction
    while(MC_ME.GS.B.S_CURRENT_MODE != DRUN_MODE);  // ME_GS Check DRUN mode has successfully been entered
}//Sys_Init

32 Views
manuelmoreno-eg
Contributor II

Thanks a lot. Very fast and efficient support fron NXP. Congratulations!

Mauel

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