I am working with MPC5777M EVM board for LIN module implement. I did clock configuration as following but I am not able to establish the connection between two LIN port over the LIN bus. Please find the following clock configuration and make me sure I am on right trace or not ? If not then please tell me what changes i will do to establish communication between two LIN port over the LIN bus ?
void system160mhz(void){
{
MC_CGM.AC3_SC.B.SELCTL = 0x01u; //connect XOSC to the PLL0 input
MC_CGM.AC4_SC.B.SELCTL = 0x01u; //connect XOSC to the PLL1 input
// Set PLL0 to 300 MHz with 40MHz XOSC reference
PLLDIG.PLL0DV.R = 0x4002100Fu; // PREDIV = 1, MFD = 15, RFDPHI = 2, RFDPHI1 = 8
MC_ME.RUN_MC[0].R = 0x00130070u; // RUN0 cfg: IRCON,OSC0ON,PLL0ON,syclk=IRC
// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0u; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50Fu; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4u) {}; // Verify RUN0 is the current mode
// Set PLL1 to 600 MHz with 40MHz XOSC reference
PLLDIG.PLL1DV.R = 0x0001001E; // MFD = 30, RFDPHI = 1
MC_ME.RUN_PC[0].R = 0x000000FE; // enable peripherals run in all modes
MC_ME.RUN_MC[0].R = 0x001300F4; // RUN0 cfg: IRCON, OSC0ON, PLL1ON, syclk=PLL1
MC_CGM.SC_DIV_RC.R = 0x00000001; //! System clock divider ratios will change with next update. Not required for Cut 1.
MC_CGM.DIV_UPD_TYPE.R = 0x80000000; //! System clock divider ratios updated on writing MC_CGM.DIV_UPD_TRIG. Not required for Cut 1.
MC_CGM.SC_DC2.R = 0x800B0000; // PBRIDGEA/PBRIDGEB_CLK at syst clk div by 12 ... (50 MHz)
MC_CGM.SC_DC1.R = 0x80050000; // SXBAR_CLK at syst clk div by 6 ... (100 MHz)
MC_CGM.SC_DC0.R = 0x80020000; // FXBAR_CLK, BD_CLK, IOP_CLK at syst clk div by 3 ... (200 MHz)
MC_CGM.SC_DC3.R = 0x80010000; // COMP/CHKR_CLK at syst clk div by 2 ... (300 MHz)
MC_CGM.SC_DC4.R = 0x800A0000; // CLKOUT at syst clk div by 11 ... (54.55 MHz)
MC_CGM.DIV_UPD_TRIG.R = 0xfeedface; //! System clock divider ratio updates triggered. Not required for Cut 1.
while (MC_CGM.DIV_UPD_STAT.B.SYS_UPD_STAT == 1) //! Wait for System Clock Divider Update Status == 0. Not required for Cut 1.
{
// wait only
}
// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS == 1u )
{
// Wait for mode transition to complete
}
while(MC_ME.GS.B.S_CURRENT_MODE != 4)
{
// Verify RUN0 is the current mode
}
MC_CGM.AC0_SC.R = 0x02000000; // Select PLL0 for auxiliary clock 0
MC_CGM.AC0_DC0.R = 0x80050000; // PER_CLK : Enable aux clk 0 div by 6 … (50 MHz)
MC_CGM.AC0_DC4.R = 0x80020000; // Enable auxiliary clocks for LIN_CLK : 0 div by 3 … (100 MHz)
// MC_ME.PCTL15.R = 0x00000000u; // Enable SIUL2 clock
//MC_ME.PCTL92.R = 0x00000000u; // Enable SIUL2 clock for LINFlexD_0.
//MC_ME.PCTL92.R = 0x00000000u; // Enable SIUL2 clock for LINFlexD_0.
}
}
