Hello,
I am doing some experiments with the e200z6 unified cache - specifically, I'm analyzing the effects of flushing and invalidating the entire cache in some application. Currently, I'm invalidating and flushing each cache line individually:
/* GreenHills compiler asm syntax */
__asmleaf void flush_inv_cache_line(unsigned int flushed_way, unsigned int flushed_set) {
%reg flushed_way %reg flushed_set
mfspr r3, l1finv0
insrwi r3, flushed_way, 5, 3
insrwi r3, flushed_set, 7, 20
li r4, 2
rlwimi r3, r4, 0, 30, 31
msync
mtspr l1finv0, r3
}
void flush_inv_cache(void) {
unsigned int i;
unsigned int j;
for (i = 0u; i < 8u; i++)
{
for (j = 0u; j < 128u; j++)
{
flush_inv_cache_line(i, j);
}
}
}
It seems the code is working correctly, but I wonder if there are more efficient ways of doing this. Is there any way to flush and invalidate the entire cache without these loops?
Best regards,
Ricardo
Solved! Go to Solution.
Hi Ricardo,
that's a good point. When the cache is invalidated using CINV bit, data are not flushed. This operation is not supported on the device. So, it could cause cache coherency issues. If you use copyback mode, the only way to flush the cache is to use L1FINV0 register and flush each cache line individually.
Regards,
Lukas
Hi,
this can be found in core reference manual for e200z6:
Regards,
Lukas
Hi Lukas,
Thanks for your answer. When reading the e200z6 documentation, I wondered if doing an invalidation in the way you show could create cache coherency issues if I use the cache in copyback mode. How does data/instruction copyback work when I set L1CSR0[CINV]?
Best regards,
Ricardo
Hi Ricardo,
that's a good point. When the cache is invalidated using CINV bit, data are not flushed. This operation is not supported on the device. So, it could cause cache coherency issues. If you use copyback mode, the only way to flush the cache is to use L1FINV0 register and flush each cache line individually.
Regards,
Lukas