I am working on CMU. I enabled all the CMUs and their interrupts. the first problem occurs when a CMU01 interrupt event is generated. then program goes into all "if, else if" conditions. as shown in the figure there are three break point. the program stops on lines respectively 126, 128, 132, 126, 128, 132...when the program stops at line 126, I look to CMU0 and CMU1 ISR registers from embedded register section. I see that there no interrupt request from CMU0 but the program still goes into CMU0's conditions. There is no error in my "if, else if" conditions as you can see. let say my condition is wrong so program goes into first "if" condition. how can it goes in to "else if" conditionwithout reentering to the CMU01_IRQHANDLER? I wrote the sequence of the flow of program above. The program goes into else if without reentering to the CMU01_IRQHANDLER.
second problem is again about CMU01 interrupt. I set the clock frequency to max frequency of system. which is 300MHz PLL1 output and 240MHz PLL0 output. CMU1 was adjusted for checking signal according to 300MHz clock signal. I set the LREF value as 30Mhz for dont get any interrupt request from CMU1 FLL. but the program still set interrupt flag of FLLI. you can see screen shot above for this issue. clock configuration is placed under this text. my question is that how can I fix this issues? did I do something wrong? Can you give information to me about that?
// Enable PLL0, PLL1 and select PLL1 as sys clk (300 MHz)
void SysClk_Init(void)
{
SIU.SYSDIV.B.SYSCLKSEL = 0; //run system clock from IRC
PLLDIG.PLL0CR.B.CLKCFG = 0; //disable PLL0
PLLDIG.PLL1CR.B.CLKCFG = 0; //disable PLL1
SIU.SYSDIV.B.PLL0SEL = 0x00; //connect XOSC to the PLL0 input
SIU.SYSDIV.B.PLL1SEL = 0x01; //connect PLL0-PHI1 to the PLL1 input
// Set PLL0 to 240 MHz with 40MHz XOSC reference
PLLDIG.PLL0DV.R = 0x40022018; // PREDIV = 2, MFD = 24, RFDPHI = 2, RFDPHI1 = 8
while(SIU.RSR.B.XOSC==0){}; //wait for stable XOSC
PLLDIG.PLL0CR.B.CLKCFG = 3; //turn on PLL0
while(PLLDIG.PLL0SR.B.LOCK==0){}; //wait for PLL0 lock
// Set PLL1 to 300 MHz with 60MHz PLL0-PHI1 reference
PLLDIG.PLL1DV.R = 0x00020014; // MFD = 20, RFDPHI = 2
PLLDIG.PLL1CR.B.CLKCFG = 3; //turn on PLL1
while(PLLDIG.PLL1SR.B.LOCK==0){}; //wait for PLL1 lock
// Select clock dividers and sources
// PLL0 SEL = 0 … XOSC selected
// PLL1 SEL = 1 … PLL0-PHI1 selected
// PERCLKSEL = 1 … PLL0 selected
// FMPERDIV = 0 … div by 2
// PERDIV = 0 … div by 2
// MCALSEL = 1 … PER_CLK selected
// SYSCLKSEL = 2 … PLL1
// ETPUDIV = 1 … div by 1
// SYSCLKDIV = 4 … div by 1
// PCS = 0 … Disabled
SIU.SYSDIV.R = 0x0500A110;
// ENGDIV = 16 … div by 32
// ECCS = 0 … PLAT_CLK selected
// EBDF = 2 … div by 3
SIU.ECCR.R = 0x00001002;
// SDDIV = 14 … div by 15
SIU.SDCLKCFG.R = 0x0000000E;
// LFCLKSEL = 0 … XOSC selected
// LFDIV = 1 … div by 2
SIU.LFCLKCFG.R = 0x00000001;
// PSDIV = 2 … div by 3
// PSDIV1M = 239 … div by 240
SIU.PSCLKCFG.R = 0x000200EF;
}
