In CMU0, CMU3, CMU4
the ISR of each fire 0x02, FLLI
What are the values should be written in their division register in order to clear the ISR FLLI bit ?
CMU0
=160Mhz*16*4/16Mhz =640
LFREF = 640*0.95 = 608 --> 0x260
HFREF = 800*1.05 = 672 --> 0x2A0
MC_CGM_AC0_DC0=0x80010000
CMU3
=80Mhz*16*4/16Mhz =320
LFREF = 320*0.95 = 304 --> 0x130
HFREF = 320*1.05 = 336 --> 0x150
MC_CGM_AC0_DC2 = 0x80000000
CMU4
=80Mhz*16*4/16Mhz =320
LFREF = 320*0.95 = 304 --> 0x130
HFREF = 320*1.05 = 336 --> 0x150
MC_CGM_AC1_DC1= 0x80000000
Solved! Go to Solution.
Hi,
be sure clock selector MC_CGM_ACn_SC is selecting right clock, I assume PLL0 configured for 160Mhz. Or what is your selections?
Then use divider to be consistent with your calculation and clock source selected.
BR, Petr
Hi,
be sure clock selector MC_CGM_ACn_SC is selecting right clock, I assume PLL0 configured for 160Mhz. Or what is your selections?
Then use divider to be consistent with your calculation and clock source selected.
BR, Petr