CMU_1 & CMU_2 are always giving FLL event occurred irrespective of the value in LFREFR

[ignatiusmichael]

Hi all,

   I am trying to configure Clock Monitoring Unit (CMU) for MPC5777C. I have configured CMU_0 to CMU_7.

all my CMU's are working as expected, except for CMU_1 which is monitoring core_clk running at 264MHz

and CMU_2 which is monitoring plat_clk running at 132MHz.

These two are always generating FLL event occurred for CMU_LFREFR as low as 0x1. How do i solve this issue?

I am calculating the LFREFR value (for core_CLK) as (264000000U * 64.0) / (f_IRCOSC * 1.05)  where f_IRCOSC is obtained by frequency metering and comes around 15.93 MHz. i am then setting the value to the register and enabling CME. following which i am clearing CMU_ISR register to reset any flags that were set before enabling. 

I have also tried giving a huge delay after and before Enabling CME but had similar results.

DEBUGGER O/P

CMU_1_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_1_FDR 00000000 FD 000000
CMU_1_HFREFR 0000045B HFREF 045B
CMU_1_LFREFR 000003F1 LFREF 03F1
CMU_1_ISR 00000002 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 01: FLL event occurred
OLRI 00: No OLR event
CMU_1_MDR 00000000 MD 000000

CMU_2
CMU_2_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_2_FDR 00000000 FD 000000
CMU_2_HFREFR 0000022D HFREF 022D
CMU_2_LFREFR 000001F8 LFREF 01F8
CMU_2_ISR 00000002 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 01: FLL event occurred
OLRI 00: No OLR event
CMU_2_MDR 00000000 MD 000000

Thanks

[petervlna]

Hi,

Please see the following calculation for LFREF:

LFREF = (L_fref * 16 *4 ) / IRC

LFREF = (264M * 16 *4) / 16Mhz = 1056

0,5% frequency spread = > LFREF = 1056*0.95 = 1003 = 0x3EBh

Try to set LFREF to 0x3EBh instead of 0x03F1

regards,

Peter

[ignatiusmichael]

Hi Peter,

Thank you for your reply.

So i tried the value that you suggested but unfortunately it still didn't work, i have attached the debugger o/p for your reference i also tried for LFREF 0x1 and 0x0 .

Debugger O/P for LFREF 0x3EB
CMU_1

CMU_1_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_1_FDR 00000000 FD 000000
CMU_1_HFREFR 0000045C HFREF 045C
CMU_1_LFREFR 000003EB LFREF 03EB
CMU_1_ISR 00000002 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 01: FLL event occurred
OLRI 00: No OLR event
CMU_1_MDR 00000000 MD 000000

CMU_2
CMU_2_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_2_FDR 00000000 FD 000000
CMU_2_HFREFR 0000022E HFREF 022E
CMU_2_LFREFR 000001F8 LFREF 01F8
CMU_2_ISR 00000002 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 01: FLL event occurred
OLRI 00: No OLR event
CMU_2_MDR 00000000 MD 000000

Debugger O/P for LFREF 0x1
CMU_1
CMU_1_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_1_FDR 00000000 FD 000000
CMU_1_HFREFR 0000045C HFREF 045C
CMU_1_LFREFR 00000001 LFREF 0001
CMU_1_ISR 00000002 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 01: FLL event occurred
OLRI 00: No OLR event
CMU_1_MDR 00000000 MD 000000

Debugger O/P for LFREF 0x0
CMU_1
CMU_1_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_1_FDR 00000000 FD 000000
CMU_1_HFREFR 0000045C HFREF 045C
CMU_1_LFREFR 00000000 LFREF 0000
CMU_1_ISR 00000000 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 00: No FLL event
OLRI 00: No OLR event
CMU_1_MDR 00000000 MD 000000

MY FCCU o/p for LFREF 0x3EB

NCF_S0 08000000 NCFSx 08000000
NCF_S1 00000C00 NCFSx 00000C00

Please help in resolving this issue.

Also for LFREF calculation the formula that you used multiplies LFREF with 0.95, whereas in my formula i was dividing by 1.05 which is the same (1/1.05 = 0.95). Is there any reason you asked me to multiply rather than divide??

[dan_teodorescu]

Hi,

I found the following description in the MPC5777C reference manual, section 19.13.7.

If the checker core and RCCU are disabled (via a DCF client), then the clock to the
checker core lake is halted to save power. Because CMU_1 and CMU_2 are
monitoring points in the clock tree inside the checker core lake, these CMUs cannot
be used if the checker core is disabled.

This may explain the observed behavior based on your MCU configuration.

Dan

[dan_teodorescu]

Hi Michael,

I am seeing the same issue as you are describing. Did you find out what was causing it?

Thanks