I have another strange problem sull'EBI: I set in OR0, APS = 1 and PS=1 in BR0. I have a bus 16-bit not multiplexed
I expect ADDRESS 31 (D_CS2 PIN) make ADDRESS 30, but it does not work well
We contacted the design person and confirmed that APS feature is implemented on mpc5777c device.
Please check the MCR, BR and OR register settings. Can you please share with me these register settings, particularly EBI_MCR[D16:31] value and D_CS2 SIU_PCR settings?
i'm sure that aps=1 is implemented, but for use this parameter on OR, it is need work also CS2 set as addres A31
If the cpu bug that not set CS2 as address A31(with APS=1 get A30) is not possible use APS parameter
In new user manual this part is not change
manual indicate cs2 as address, but note 3 only data.
the correct value is address and not data.
I have been just confirmed from the designer that table 27-3 entry for D_CS2 in non-muxed 16-bit mode is wrong and it is not connected to ADDRESS but rather is hooked to DATA.
So unfortunately, APS feature is not useful in this mode.
Ticket for potential errata/RM update has been created. We're sorry for the inconvenience it might bring to you.
i have a suspicion and with a program test is very probable:
in your user manual:
Table 27-3. Function of EBI pins for supported configurations
Non-muxed 16-bit mode PIN D_CS2 is Address 
but with test is an Data, not work as ADDRESS!!!!!
Is possible a this BIG BUG IN CPU????????
I do not understand if the transition from Freescale to NXP is the cause of tecnological and support degradation on MPC5777C family. it is 'absurd not to have an answer on three problems in many months
1)test burst is easy on MPC5777C EVB
2)test dual core memory coerency, if i use SRAM on EBI is easy for NXP in EVB
3)test APS=1 and D_CS2 if has address is very easy
I am apologizing for not hearing from us. I can understand the inconvenience this might bring to you. Just for explanation:
1) This has been escalated relatively long time ago, but assigned person has been changed recently as previously assigned person probably left the company. Now it is assigned to another person. I have already urged him for solution.
2) This has been stucked on my side as I just forgot on your other thread. Once again sorry for that. When you give me details I will work on that with priority.
3) This is in progress on application engineer's side, I have also reported this in relation to obvious discrepancy in our RM where it is stated that D_CS2 pin function is Address and note 3 before Table 27-3 says it is basically Data. In normal circumstances this pin is not used as 16-bit or 32-bit memories does not connect this address lines so even in case it would not work as expected probably nobody would notice. It must be somehow solved and will be.
In general you are dealing with urgent issues I would rather recommend to create a case for it:
Thanks for undertanding
NXP intends to revise the 5777C mask, settling the problems of the CS2 pin, burst problem and the Platform coherency Unit in dual core mode when core 1 work in memory on EBI?
You have told in thread 438364:
“I will prepare some documentation and C example.”
Have you created such one? Could you share it with us?
I have no idea what application engineers/designers will decide to do with that but we really need as much information as possible from your side.
If you already create a case how I recommended in previous answer, please give me its number. Thanks
for the PCU problem I have try to generate a simple C code, becuse is not easy with two core and EBI.
However, in testing I found that the PCU registers do not even report the overflow in the specific bits for example
for APS=1 i not have soluction or workaround