About MPC5744P Access Reserve Address

[jasoncao]

Hi Everyon,

     I have a problem about access reserve address.There is some reserve address in the MPC5744P Memory Map,Such as 0x00,0x40060000 ,0xFFFFFFFF.The Error Access will casue the machinecheck interrupt IVOR1 sometimes,but sometimes cause Data Storage Interrupt IVOR2.Anyone could tell me the specific rules of the interrupt trigger for access reserve address? Thanking Everyone!LoL

[lukaszadrapa]

Hi,

it depends on state of MSR[EE] and MSR[ME] bits. Take a look at this application note, Table 4 and Table 5:

http://www.nxp.com/files/microcontrollers/doc/app_note/AN5200.pdf

It doesn't matter if the error is caused by ECC error or by access to reserved address space. It's just about general bus error.

Regards,

Lukas

[jasoncao]

Hi Lukas,

     I find that who affect the trigger interrupt.At the Normal State,the bus error will trigger Machine Check Interrupt;the bus error will trigger data storage Interrupt when I set the MPU to restrain the cache for some memory space.

[lukaszadrapa]

Hi,

yes, the behavior/reaction of SMPU is slightly different. But it is explicitly mentioned in reference manual in SMPU chapter:

Lukas

[jasoncao]

Hi Lukas,

     Thank you very much! :smileyhappy:

[jasoncao]

Hi Lukas,

     Thank you very much.The CPU of MPC5744P is E200Z4.There's not affect between the MSR[EE] and the CPU Interrupt IVOR1/2  who will be trigger refer to the Table 5 at AN5200.

     I try to test the relation between the MSR[EE] /MSR[ME] and the Trigger Interrupt.But I draw a blank.