This is my code ,Why I cannot start my AD Conversion !
when I executate ADC.MCR.B.NSTART=1; In register This bit Cannot be set.
Could you please tell me where has problems? Thanks in advance for your kindly help!
#include "MPC5604B_0M27V_0102.h" /* Use proper header file */
uint16_t Result[3]; /* ADC conversion results */
uint16_t ResultInMv[3]; /* ADC conversion results in mv */
void initModesAndClock(void) {
ME.MER.R = 0x0000001D; /* Enable DRUN, RUN0, SAFE, RESET modes */
/* Initialize PLL before turning it on: */
CGM.FMPLL_CR.R = 0x02400100; /* 8 MHz xtal: Set PLL0 to 64 MHz */
ME.RUN[0].R = 0x001F0074; /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
ME.RUNPC[1].R = 0x00000010; /* Peri. Cfg. 1 settings: only run in RUN0 mode */
ME.PCTL[32].R = 0x01; /* MPC56xxB/P/S ADC 0: select ME.RUNPC[1] */
ME.PCTL[68].R = 0x01; /* MPC56xxB/S SIU: select ME.RUNPC[1] */
/* Mode Transition to enter RUN0 mode: */
ME.MCTL.R = 0x40005AF0; /* Enter RUN0 Mode & Key */
ME.MCTL.R = 0x4000A50F; /* Enter RUN0 Mode & Inverted Key */
while (ME.GS.B.S_MTRANS) {} /* Wait for mode transition to complete */
/* Note: could wait here using timer and/or I_TC IRQ */
while(ME.GS.B.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */
}
void disableWatchdog(void) {
SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */
SWT.SR.R = 0x0000d928;
SWT.CR.R = 0x8000010A; /* Clear watchdog enable (WEN) */
}
void initPeriClkGen(void) {
/* Use the following code as required for MPC56xxB or MPC56xxS:*/
CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
}
void main (void) {
vuint32_t i = 0; /* Dummy idle counter */
initModesAndClock(); /* Initialize mode entries and system clock */
disableWatchdog(); /* Disable watchdog */
initPeriClkGen(); /* Initialize peripheral clock generation for DSPIs */
SIU.PCR[24].R = 0x2000; /* MPC56xxB: Initialize PB[8] as ANS0 */
SIU.PCR[25].R = 0x2000; /* MPC56xxB: Initialize PB[9] as ANS1 */
SIU.PCR[26].R = 0x2000; /* MPC56xxB: Initialize PB[10] as ANS2 */
ADC.MCR.R = 0x80000000; /* Initialize ADC0 for one short mode */
ADC.NCMR[1].R = 0x00000007; /* Select ANS0:2 inputs for conversion */
ADC.CTR[1].R = 0x00008606; /* Conversion times for 32MHz ADClock */
ADC.MCR.B.NSTART=1; /* Trigger normal conversions for ADC0 */
while (1) {
while (ADC.CDR[33].B.VALID != 1) {}; /* Wait for last scan to complete */
Result[0]= ADC.CDR[32].B.CDATA; /* Read ANS0 conversion result data */
Result[1]= ADC.CDR[33].B.CDATA; /* Read ANS1 conversion result data */
Result[2]= ADC.CDR[34].B.CDATA; /* Read ANS2 conversion result data */
ResultInMv[0] = (uint16_t) (5000*Result[0]/0x3FF); /* Converted result in mv */
ResultInMv[1] = (uint16_t) (5000*Result[1]/0x3FF); /* Converted result in mv */
ResultInMv[2] = (uint16_t) (5000*Result[2]/0x3FF); /* Converted result in mv */
i++;
}
}
Hi Li weimin,
Your code seems to work fine. Explanation of your question is described in reference manual for Bolero in chapter 25.3.1.2 on page 594.
http://cache.freescale.com/files/32bit/doc/ref_manual/MPC5604BCRM.pdf
The MSR[NSTART] status bit is automatically set when the normal conversion starts. At the same time the MCR[NSTART] bit is reset, allowing the software to program a new start of conversion. In that case
the new requested conversion starts after the running conversion is completed.
Regards,
Martin