Hello everyone,
There are two photos attached below from MPC5777C reference manuel.
If we look at the photo of DFFF bit, it tell us that DFFF bit is set when the number of converted datawords in the FIFO is equal to or more than number indicated by FCR[FTHLD].
Nevertheless, we move on second photo showing us the description of FTHLD bit located on FCR register, it demonstrates us that FIFO full event flag(DFFF) is set when the number of datawords in the data FIFO is greater than the value in FTHLD field.
There is a discrepancy between these two descriptions. When does DFFF flag be set?
