Can anyone suggest a reason as to what's wrong with this attempt to configure the SWT on a 56xx device.
On entry to the code SWT.CR.R = 0xFF00010A - so watchdog is disabled and SLK is cleared.
#define SWT_UNLOCK1 0xC520
#define SWT_UNLOCK2 0xD928
#define SWT_5MSTIMEOUT 0x13880 /* 16MHz Internal osc..@5ms timeout => 16MHz/200 = 80000 = 0x13880 */
#define SWT_SLK 0x00000010 /* Mask for software lock bit */
#define SWT_WEN 0x00000001 /* Mask for watchdog enable bit */
/* Routine to setup software watchdog timer */
/* If watchdog is disabled - set it up, otherwise leave it alone */
if (!(SWT.CR.R & SWT_WEN))
{
if (SWT.CR.R & SWT_SLK)
{
/* Soft lock bit is on - unlock the control register */
/* Unlock the control register */
SWT.SR.R = SWT_UNLOCK1;
SWT.SR.R = SWT_UNLOCK2;
}
/* Wait here for SLK to clear */
while(SWT.CR.R & SWT_SLK);
/* CR should now be writable */
SWT.CR.R |= SWT_WEN;
/* Set timeout interval */
SWT.TO.R = SWT_5MSTIMEOUT;
}
On exit of this code, the SWT.TO register has been updated, but no matter what I do to write to SWT.CR (including, for instance SWT.CR.R = 0xFF00010B;) the watchdog remains disabled.
Any idea why this is?
Thanks for any suggestions.
Solved! Go to Solution.
Hi,
This is because the debugger by default disable SWT.
Enable it in debug options of debugger or run your code wihtout debugger at all.
Peter
Hi,
This is because the debugger by default disable SWT.
Enable it in debug options of debugger or run your code wihtout debugger at all.
Peter