MPC5xxx Knowledge Base

cancel
Showing results for 
Search instead for 
Did you mean: 

MPC5xxx Knowledge Base

Labels

Discussions

Sort by:
Hello    If you want to do nothing on MCU, no-operation is used generally.     Additional mnemonics are provided for the preferred forms of no-op, like nop, e_nop, se_nop. (Where the semantics are similar but the binary encoding differ, the standard mnemonic is typically preceded with an e_ to denote a VLE instruction. To distinguish between similar instructions available in both 16- and 32-bit forms under VLE and standard instructions, VLE instructions encoded with 16 bits have an se_ prefix.)    When you compile these code within IDE, you can get the results as below. The code could run correctly except __asm__ ( "nop" ).  Some MPC5xxx will stop at  __asm__   ( "nop" ).    "nop"         gives Book E NOP instruction which isn't valid on VLE only cores. "e_nop"     gives 32bit VLE instruction. "se_nop"   gives 16bit VLE instruction. Based on the summary within AN4802 (thanks for Randy Dee's working), Qorivva MPC57xx e200zx Core Differences, Book E is not supported by MPC57xx. VLE instruction set is supported only.   This is the reason that user should use "e_nop" or "se_nop" except "nop" on MPC57xx or S32R2xx. Cheers! Oliver
View full article
******************************************************************************** * Detailed Description: * * Purpose of the example is to show how to intentionally generate FCCU fault * causing reset either directly or by FOSU (simulating by non-handled FCCU * fault). Example configures FCCU, then an error is injected with using of * Noncritical Fault Fake register and after re-booting reset cause is evaluated. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************
View full article
Hi     Migrate the code from MPC5775K to S32R274.     Tested on S32R274 EVB with S32 Design Studio for Power Architecture Version 2.1.     Unzip password: nxp Cheers Oliver
View full article
How to get latest MCAL HF version from your NXP website account if you have already registered and applied MCAL SW package.   Access www.nxp.com, login with your account            
View full article
******************************************************************************** * Detailed Description: * * Application performs basic initialization, setup PLLs. * DSPI_A is configured as master using DMA to send/receive 8 words. * * Two DMA descriptors are initialized: * - TCD[32] master transmit * - TCD[33] master receive * * * EVB connection: * * Do external loopback to connect SOUT to SIN * * PM6 ... SCKA * PM7 ... SINA * PM8 ... SOUTA * PM13... PCSA0 ** * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 3N45H * Fsys: PLL1 = core_clk = 260MHz, PLL0 = 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * *********************************************************************************
View full article
Hi,    Please update your Cyclone Flash Programming Algorithms for MPC57xx through the link.      http://www.pemicro.com/support/flash_list_menu.cfm     Older code algorithms includes area of HSM. If there are ECC errors in these blocks, the device may stuck in reset. During reset, the SSCM module searches for valid boot header. If it reads corrupted data from HSM blocks, it will not exit the reset.     Newer should be with “ NO_BASE_ADDRESS=00F90000/ ”   https://community.nxp.com/thread/444748   Failed sample waves on PORST vs RESET are as below.    Algorithms in S32DS_Power_v2_1 and S32DS_Power_v2017_R1 are good.     Regards Oliver
View full article
******************************************************************************** * Detailed Description: * * Example shows how to trigger ADC conversion on falling edge of PWM signal. * eMIOS ch1 is set to SAIC mode and a flag generated on selected edge detection * triggers BCTU channel which starts conversion of ADC1 ch9. On this channel * the board's trimmer is connected. * * EVB connection: * * J3.1 .. PA[1] - connect external PWM signal * J3.3 .. PA[2] - toggled in BCTU interrupt after ADC measurement * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * Maskset: 0N78S * Target : FLASH * Fsys: 160 MHz PLL * Debugger: Lauterbach * ******************************************************************************** Revision History: 1.0 Nov-5-2019 Petr Stancik Initial Version *******************************************************************************/
View full article
******************************************************************************** * Detailed Description: * Initializes and calibrates eQADC module and cyclically converts choosen * channel, displaying it into terminal window. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PS0  - ANA17 *                                                       PS1  - ANA18 *                                                       PS2  - ANA19 *                                                       PS3  - ANA20 * ********************************************************************************
View full article
******************************************************************************** * Detailed Description: * * eMIOS0 ch0 is set to SAIC mode generating interrupt on falling edge. * The IGF ch16, connected to eMIOSch0, is set to filter low pulses <1.5us * Intergation filter type is used for falling edge with given threshold. * eMIOS interrupt is called if input signal low pulse is longer than 1.5us. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * * eMIOS ch0 (PortG P14-16)--> connect external pulse signal * ********************************************************************************
View full article
******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed * frequency * * User can choose, which low power mode should be entered. There is LPU_MODE * macro defined, which allows to choose STOP, STANDBY or LPU_RUN mode. * * If LPU_RUN mode is selected, user can use macro LPU_STOP_SLEEP_STANDBY, * which allows to choose LPU_STOP, LPU_SLEEP or LPU_STANDBY mode. * * Ther is also RTC initialized, which wakeup microcontroller using WKPU after * 5 seconds from some of the LPU is entered. RTC uses FIRC as a source clock, * so FIRC must be enabled in all low power modes. * * * Modified files: mem.ld, sections.ld, startup.s, added file z2_restart.s * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574xG Motherboard * MCU:             PPC5748GMMN6A 0N78S * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 to A1 *                    USER LED2 to A2 * * * ********************************************************************************
View full article
******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for QOM and FPM. * Connect these pins by wire. Output wave is generated on chnl ETPUB0 (QOM0) * and its frequency is measured on the chnl ETPUB1 (FPM0). * TCR counter frequency is 64MHz, output wave configured as 1MHz ( expected * frequency measured by FPM. Window size is 28us (0x400) thus number of * measured pulses is 28 (27 initally). * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************
View full article
******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts and NMI for * WKPCFG pin (GPIO213). * User needs to connect ETPUC9 pin to user switch and general purpose output * ETPUA30 to user LED 1: * ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) * Jumper J523 position 1-2 needs to be OPEN! * * If rising edge is detected (i.e. button is pressed), machine check exception * is triggered and LED1 on is toggled. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  WKPCFG  (PortC P10-4)  --> USER_SWITCHES (P6-4) *                  Jumper J523 position 1-2 needs to be OPEN! ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.0  May-22-2019  David Tosenovjan  Initial version                            *******************************************************************************/
View full article
******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts. STM_0 channel 0 is initialized to generate 100ms * periodic interrupt. Notice that STM is free running up counter, so it's * necessary to add calculated value to compare register each time in ISR handler. * * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             SPC5744PGMMM9 1N15P * Fsys:            200 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************
View full article
******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI1 module is configured as a master, DSPI2 module is configured as a slave. * First, response of slave is initialized by writing to PUSHR register of DSPI2. * Second, we write PUSHR register of DSPI1 to send data from master. * Once data are received on both master and slave, data are read from POPR. * ------------------------------------------------------------------------------ * Test HW:         MPC5746R-176DC, MPC57xx Motherboard * MCU:             PPC5746R 1N83M * Fsys:            PLL 200MHz * Debugger:        Lauterbach Trace32 * IDE:             S32DS for Power 2017.R1 * Target:          internal_FLASH (debug mode, debug_ram mode) * EVB connection: * Connect PA13 (P8.14) to PS11 (P27.12) * Connect PA10 (P8.11) to PS10 (P27.11) * Connect PG12 (P14.13) to PS13 (P27.14) * Connect PG13 (P14.14) to PS7 (P27.8) * ********************************************************************************
View full article
******************************************************************************** * Detailed Description: * Test HW:  MPC57xx + S32R274RRUEVB * Maskset:  1N58R * Target :  internal_FLASH * Fsys:     240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 ******************************************************************************** Revision History: 1.0     Apr-02-2019     b21190(Vlna Peter)  Initial Version 1.1    Apr-03-2019     b21190(Vlna Peter)  Added SWT reset reaction *******************************************************************************/ This example demonstrated the reset trigger on first SWT_2 timeout. Following screens shows the reset source after code execution in standalone mode and debugger connection afterwards:
View full article
* Detailed Description: * Test HW:  MPC57xx + S32R274RRUEVB * Maskset:  1N58R * Target :  internal_FLASH * Fsys:     240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * This example provides user with a configuration of clocks for all cores and all peripherals. * Peripherals and cores are supplied by maximum available clock configuration from PLLDIG block. ******************************************************************************** Revision History: 1.0     Apr-02-2019     b21190(Vlna Peter)  Initial Version *******************************************************************************/
View full article
******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive a CAN message  Baudrate to is set to 500kbps. In this config, RXFIFO is used to receive a messages. 16 filter elements are defined in the RXFIFO table. Both standard and extended IDs are used. MB10 is moreover used to receive a message with given standard ID. MB11 is used to transmit a message upon button press. The callback function is installed as well and is it called each time message is received in MB10, RXFIFO or message is transmitted. NOTE! Termination resistor (120Ohm) have to be placed on transceivers output             12V power supply must be connected. ------------------------------------------------------------------------------ Test HW: DEVKIT-MPC5748G Maskset: 0N78S Target : FLASH Fsys: 160 MHz PLL ********************************************************************************
View full article
******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash * and Flash over Flash. The remapping is visible only in mirrored flash address * space. Normal address space is not affected. To see effect of the remapping, * read the comments and watch following addresses in debugger before and after * executing Overlay() function: * * Flash over Flash test case: * 0x0104_0000 * 0x0108_0000 * 0x0904_0000 * 0x0908_0000 * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * ------------------------------------------------------------------------------ * Test HW:         DEVKIT-MPC5748G * MCU:             PPC5748GSMKU6 0N78S * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH (debug mode) * EVB connection:  NA * ********************************************************************************
View full article
This tool simplifies CAN bit timing calculation for CAN modules (FlexCAN, MCAN) available on MPC5xxx and S32K1xx families.   Enter input parameters into light green cells.   Device and Transceiver are selected from pull-down menus.        By selecting Transceiver, propagation delay parameter is also loaded, but can be simply overwritten by user value. Rest of parameters can be modified directly upon user needs. The tool lists possible setting together with register view. A recommended setting is highlighted. Three criteria are used for recommended values selection - desired sample point - highest fcpi accuracy - same prescalers for nominal and data phases, if CAN FD is calculated   For sure other setting can be selected, if needed, by clicking on respective line in list.   Note: Macros have to be enabled! BR, Petr
View full article