******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM to generate independent * PWM signals from Submodule0. The PWMX output is set for 50% duty. * PWMA/PWMB outputs vary its duty cycles. * The DMA module is used to reload VAL2-5 registers. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * P11.10 - D[9] .. FlexPWM X[0] output * ********************************************************************************

******************************************************************************** * Detailed Description: * Example demostrates MCU behaviour when single bit RAM ECC error occurs by * intentional ECC error injection. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * PIT channel 0 is used to generate 1sec interrupt where PA0 pin is toggled. * * ------------------------------------------------------------------------------ * Test HW:  MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset:  0N78H * Target :  RAM, internal_FLASH * Fsys:     600 MHz PLL1 with 40 MHz crystal reference *               core2 at 200MHz generated from PPL1 * Terminal: None ********************************************************************************

WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!!   WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5644A. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems   WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS   The example consists of 2 parts and document describes how to access censored device via JTAG with using of PeMicro or Lauterbach debugger:   1) MPC5644A-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code re-programs content of shadow flash to enable censorship. * Succesful operation is confirmed by notices in terminal window on eSCI_A * (19200-8-no parity-1 stop bit-no flow control). * After power-on-reset the device is censored with private password * 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be allowed by enabling * debug of censored device as decipted in attached pdf document. Shadow flash * re-programming code must be executed from internal RAM. * ------------------------------------------------------------------------------   2) MPC5644A-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5644A-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. Programmed password is 0xFEED_FACE_CAFE_BEEF. * MPC5644A_run_from_ram.cmm script does it by command * SYStem.option.keycode 0xFEEDFACECAFEBEEF. * Then run this code to uncensor the device. Succesful operation is confirmed by * notices in terminal window on eSCI_A (19200-8-no parity-1 stop bit-no flow * control). After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes and display notice via UART terminal. It calculates temperature * using TSENS and printes it to the terminal window. * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed frequency (48MHz) * Setup SIU, and demonstrate frequency modulation. * ------------------------------------------------------------------------------ * Test HW:        XPC560B 64LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             SPC5602D * Cut:               1M18Y * Fsys:             48 MHz * Debugger:     Lauterbach Trace32 * Target:           internal_FLASH * EVB clkout pin : Port J7 - pin 0 * ********************************************************************************

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test is performed in this example: after initialization, SMPU_1 * configuration is changed to disable write access to last 4kB of RAM for * Process ID 1. Write acess is allowed for Process ID 0. * If this area is written by CPU while the Process ID is 1, exception will * occur due to access violation. * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

Detailed Description: Demo application performs I2C communication with externally connected temperature sensor LM75B. Obtained values and processed and displayed on MPC5606S-DEMO-V2 board’s TFT panel. Application uses standard Graphics Libraries for MPC5606S for simple graphic output that is managed in mc_base.c module only. I2C communication is managed with using of own two layer driver where low-level driver consisting of I2C_0.c and I2C_0.h - these can be used for any device connected to I2C_0 module. Middle-level driver layer consist of I2C_LM75B.c and I2C_LM75B.h and it is specific to LM75B device. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + LM75BD MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:   For complete project you may see following link: Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI

Detailed Description: Demo application performs I2C communication with externally connected external real time clock/calendar PCA8565. Obtained values and processed and displayed on MPC5606S-DEMO-V2 board’s TFT panel. Date and time may be set up by demo board’s buttons (SW2-SW6). Application uses standard Graphics Libraries for MPC5606S for simple graphic output that is managed in mc_base.c module only. I2C communication is managed with using of own two layer driver where low-level driver consisting of I2C_0.c and I2C_0.h - these can be used for any device connected to I2C_0 module. Middle-level driver layer consist of I2C_PCA8565.c and I2C_PCA8565.h and it is specific to PCA8565 device. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + LM75BD + HIH-5030 + PCA8565 sensors MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:   For complete project you may see following link: Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI

******************************************************************************** * Detailed Description: * * * This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules. * The setting is selected in the way to have a PWM output signal synhronized with * SWG output signal. This is necessary for resolver usage in motor control appls. * The CTU_0 is triggered from FlexPWM_0's. The PMWB output rising edge is used here. * The CTU generates the eTIMER1_TRG signal, that is a trigger signal for the * SGEN module. The delay between PWMB and SGEN trigger is changed so you can see * the generated sinusoidal signal change phase against the PWMB output. * * See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0, * AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO). * * This example is set for 9.765625KHz SGEN/PWM frequency. * * Note  because the SGEN trigger input is an asynchronous signal, it must be held high * for at least 2 SGEN clock cycles in order to capture the input trigger. * As the CTU generates the trigger as a pulse of single CTU clock width, the CTU clock must be * half of the SGEN clock at least. * * Use the AUX0_clk_DIV0 to test this behaviour. * * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P11.8 - D[7] .. SGEN output *          connected to FEC PHY's MIIMODE input on motherboard, *          to see full amplitude remove J26    * * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * * ********************************************************************************

Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI Simple weather station demo using 2 external sensors and  external real time clock/calendar   For detailed description SEE ATTACHED document. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + LM75BD + HIH-5030 + PCA8565 sensors MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:  1) Temperature sensor LM75B:                        J51.40 - F[6] -> LM75B SDA                        J51.43 - F[7] -> LM75B SCL                        J52.1  - 3.3V -> LM75B Vcc                        J50.1  - GND  -> LM75B Gnd                   2) Humidity sensor HIH-5030:                        J52.1  - 3.3V -> HIH-5030 Ve+                        J50.1  - GND  -> HIH-5030 Ve-                        J50.1  - ANS0 -> HIH-5030 Out                   3) External Real Time Clock:                        J51.40 - F[6] -> PCA8565 SDA                        J51.43 - F[7] -> PCA8565 SCL                        J52.1  - 3.3V -> PCA8565 Vcc                        J50.1  - GND  -> PCA8565 Gnd                                        *******************************************************************************

******************************************************************************** * Detailed Description: * Example demonstates Shifted PWM generating via eMIOS. * The shift is 25% duty cycle. * ------------------------------------------------------------------------------ * Test HW:  MPC5644A + XPC564A minimodule + XPC56XX mother board * Maskset:  OM14X * Target :  Internal Flash * Fsys:     16MHz IRC * * EVB settings: * PJ8 pin 0 is eMIOS CH[0] * PJ8 pin 2 is eMIOS CH[2] ******************************************************************************** Revision History: 1.0     Jun-23-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * This example shows how to use eDMA for transfering 32-bit data multiple time using minor loop from internal flash to SRAM memory as well as how to configure AIPS (peripheral bridge) to grant eDMA access to peripherals. * * For closer details on how eDMA works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The constant stored in internal flash is transfered via eDMA to SRAM memory. * Initialization functions are AIPS_0_Init for peripheral bridge and DMA_0_Init. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 0N15P * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5604EEVB64 * MCU:             PPC5604EEMLH 0N10D * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            40 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  JP17 connected to J38.7 (ADC CONN), jumpers J7,J8 position *                  2-3 fit SCI tx and rx connected * ********************************************************************************

******************************************************************************** * Detailed Description: * Inject and handles HVD and LVD faults. Application also configures FCCU_F pins * to see possible faults externally - normally these two pins toggles antiphase, * in case error these pins toggles inphase. If you step the code not allowing * alarm interrupt to be handled on time, device goes to safe mode and FCCU_F * pins toggles in phase. * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  FCCU_F0 and FCCU_F1 connected to the scope - pay attention to *                  J16 and J18 jumpers on mini-module (FCCU_F0 and FCCU_F1). * ********************************************************************************

This document shows, how to use CodeWarrior 10.6 to program QSPI flash for Power Architecture microcontrollers.   1) Create new project for appropriate microcontroller. 2) Open Debug configuration and duplicate one of the target.   3) Rename duplicated target (optional) 4) Choose the duplicated (renamed) target and click Edit button in Target settings tab.   5) In new screen, click Advanced Programming Options.   6) Check Use Alternative Algorithm and choose the algorithm you want to use. Algorithms are place in CodeWarrior installation folder. Full path is CodeWarrior_installation_folder\MCU\bin\plugins\support\EPPC\gdi\P&E\   7) On the screen Debug configuration, choose the file you want to program to QSPI flash.   Click Apply and Debug.

******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  eSCI_A is USBtoUART bridge (connector J21) * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** Detailed Description: Example shows configuration of SIUL External interrupts using SDK driver. EIRQ0 (PA3) and EIRQ11 (PE12) are configured for detecting rising edge. Those pins are connected to switches SW1 and SW2 on DEVKIT board. EIRQ1 (PA6) is configured for detecting falling edge. Within its interrupt routines a LEDs are toggled upon edge detecting. See PinSetting component for pins configuration within "Routing" and "Functionals Properties" tabs. To see falling edge on PA6 just connect pin (J2.1) to GND shortly. * ------------------------------------------------------------------------------ * Test HW:         DEVKIT-MPC5748G * MCU:             PPC5748GSMKU6 0N78S * Target:          Debug_FLASH * EVB connection: * Compiler:        S32DS.POWER.2017.R1 * SDK release:     S32_SDK_S32PA_BETA_2.9.0 * Debugger:        S32DS, Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date        Author       Description of Changes 0.1 Jun-13-2019 Petr Stancik Initial version *******************************************************************************/