******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:         This example demonstrate SWT functionality *                   On SWT timeout it sent signal to FCCU where is short *                   functional reset reaction on SWT timeout configured *                   FCCU then sent signal to RGM module which triggers short *                   functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1        Mar-24-2015       b21190(Vlna Peter)  Added SWT short reset *******************************************************************************/

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0 and TSENS1 are read from Test Flash and * ADC0/ADC1 is set to measure Vbg and TSENS outputs. * Calculated internal temperature can be desplayed on the Terminal. * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). You should get following text * (with different values for sure) * * TSENS0/TSENS1 temperature measurement * press any key to continue... * * Calibration constants read from Test Flash * * TSENS0                           TSENS1 * * K1 = 429                         K1 = -220 * K2 = -5785                       K2 = -5767 * K3 = -12800                      K3 = -12736 * K4 = 45                          K4 = 45 * *      K1 * Vbg_code * 2^-1 + K2 * TSENS_code * 2^3 * T = ------------------------------------------------------------------------- / 4 - 273.15 [degC] *     [K3 * Vbg_code * 2^2 + K4 * TSENS_code] * 2^-10 * * Vbg0_code      = 1502               Vbg1_code      = 1502 * TSENS0_code = 2002               TSENS1_code = 1988 * * TSENS0 temp = 34.57 degC         TSENS1 temp = 36.78 degC * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction/data cache and enabling of branch prediction. * Example suppose MCU is configured for LSM (Lock-step mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

This session will explain how Freescale can enable customers to develop 76-81 GHz short and long range radar applications using the MPC577xK MCU, it will explain the concepts of the radar algorithms, including practical aspects such as SDADC or MIPI CSI sampling, Chirp Generation, Data Compression, R,V FFT, Detection and Tracking algorithms, and the benefits of the new Freescale IP that can allow them to improve their system resolution and accuracy. In this session customers will take away a detailed understanding of how to develop fast modulation radar systems using the MPC577xK MCU including the BOM cost advantages it also brings.

******************************************************************************** * Detailed Description: * This example shows, how to initialize FlexCAN modules for simple transmission * and reception using RX interrupt. Both modules are configured for 100kbit/s * bit rate. CAN_0 module transmits message using MB0. CAN_1 module receives * message using interrupt via MB0. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574XG - Motherboard * MCU:             PPC5748GMMN6A 1N81M * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  Connect jumpers J15 and J16 on motherboard *                    Connect P14 H to P15 H *                    Connect P14 L to P15 L * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the FlexCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. * Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs. * * In this config, CAN_0 transmits a message. CAN_1 receives the message. * * EVB connection: * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * NOTE! Termination resistor (120Ohm) have to be placed on transceivers output * * ------------------------------------------------------------------------------ * Test HW:  X-MPC574xG-324DS + X-MPC574XG-MB * Maskset:  1N81M * Target :  FLASH * Fsys:     160 MHz PLL * ********************************************************************************

Detailed Description:  Initializes the MCU including the FlexCAN peripherals.  Configures the FlexCAN to transmit and receive a CAN message.  In this config, CAN_0 transmits a message. CAN_1 receives the message.  CAN_0 MB8 is configured to send data each 1sec.This interval is generated by PIT.  CAN_1 RXFIFO is configured to receive a message and interrupt for MB5 is enabled.  To connect FlexCAN0 module (MCU's PB0/PB1 pins) to the motherboard's transceiver  with J5 CAN DB9 connector you have to:  - connect J17 2-6 on daughter board  - connect J17 5-3 on daughter board  This should be done as default    To connect FlexCAN1 module (MCU's PA14/PA15 pins) to the motherboard's transceiver  with J6 CAN DB9 connector you have to:  - connect J37 2-3 on motherboard  - connect J38 2-3 on motherboard  Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1  Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2  Terminate the CAN bus by connecting a 60 ohm resistor between CANH and CANL  To see LED toggling connect P8.1 to USER LED (P7.x)  ------------------------------------------------------------------------------  Test HW:  MPC5744P EVB  Maskset:  1N65H  Target :  RAM, internal_FLASH  Fsys:     200 MHz PLL with 40 MHz crystal reference

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************

******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * ------------------------------------------------------------------------------ * Test HW:        X - PC5748G - MB (rev C) * MCU:             PPC5748GMMN6A * Maskset:       1N81M * Fsys:             160 MHz * Debugger:     Lauterbach Trace32 *             * Target:     Internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example gives possible implementation of input signal period/freq measurement. * eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter * value on rising/falling edge of input signal. The FIFO is set to 2 entries * and ICF2 is monitored. Free-running mode is used here. * * eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter.   * EVB connection: *   P8.2  - A[1]  .. eTimer0 channel1 input signal *   P8.1  - A[0]  .. GPIO output, used to show measurement period * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * connect pulse signal to the P8.2. * See results on PC terminal (19200, 8N1, None). * Change freq/duty of input signal. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal SRAM (user must choose it in the option at the end of * main function). * Error Injection Module is used to generate a non-correctable (or single-bit) * ECC error in RAM. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

******************************************************************************** * Detailed Description: * This SW provides the example of clearing of FCCU faults. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference + FCCU fault clearing example code. * ******************************************************************************** Revision History: 1.0     Jan-05-2016     nxa13250(Vlna Peter)  Initial Version *******************************************************************************/

This example enters the MCU into STANDBY0 low power mode and wakes up to backup SRAM. The WKPU6 (PE[0]pin) is used to wake up the MCU.   Regards, Petr   ******************************************************************************** * Detailed Description: * * On the EVB use KEY2 to enter Standby. * Use KEY1 to wake up from Standby to a code in backup SRAM. * * In RUN mode the LED1 blinks very fast, second core toggels LED3 * In STANDBY all LEDs are off. * The wakeup code blinks LED1 and LED2 slowly. * * The macro WKP_CORE is used to select which core is used after MCU wakes up. * When z4 core is selected, it is also necessary to set the MMU otherwise exception * is generated when uncovered memory area is accessed. * This is not needed for z0 core due to lack of the MMU.  * * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH * Fsys:     120 MHz PLL0 ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop (by second core), initializes and display notice via UART terminal and * then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC567XKIT516 it initializes EBI for mounted external SRAM device. * * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  ETPUC0(J24-0) -> USER_LED_8 (J5-8) *                  ETPUC1(J24-1) -> USER_LED_7 (J5-7)(to see blinking LEDs) * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows possible implementation of frequency and duty cycle * measurement with the help of eMIOS module. * Two eMIOS channels are used and set to IPWM and IPM modes. The first channel * measures the positive pulse width and the second channel measures the period. * * EVB connection: * PJ7.5 to PJ7.6 ... connect external pulse signal to this * * See result on PC terminal (9600, 8N1) * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************     BR, Petr

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example gives possible implementation of input signal period/freq measurement. * eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter * value on rising/falling edge of input signal. The FIFO is set to 2 entries * and ICF2 is monitored. Free-running mode is used here. * * eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter. * * DMA is used to read CAPT1/2 registers and form 32bit values used in calculation. * * EVB connection: *   P8.2  - A[1]  .. eTimer0 channel1 input signal *   P8.1  - A[0]  .. GPIO output, used to show measurement period * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * connect pulse signal to the P8.2. * See results on PC terminal (19200, 8N1, None). * Change freq/duty of input signal. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************   NOTE: It cannot be used with MPC5642A device, only with MPC5644A and MPC5643A !   For MPC5642A device, use following project instead of attached one: Example XPC5642AKIT PinToggleStationery CW10.6

With author's permission I am publishing presentation comparing e200 cores to each other and describing them in detail.   Document was created in year 2010, thus it does not deal with cores subsequently used with MPC57xx devices.   Thanks to Robert Moran for his great job.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection: * * It is necessary to remove both J32 jumpers and also both J35 jumpers. * * Connect J32.2 to PC9 (CAN_0 TX) * Connect J32.4 to PC8 (CAN_0 RX) * * Connect J35.2 to PE5 (CAN_1 TX) * Connect J35.4 to PG14 (CAN_1 RX) * * Connect CAN P5.2 to CAN2 P4.2 (CAN_0 and CAN_1 CANL) * Connect CAN P5.1 to CAN2 P4.1 (CAN_0 and CAN_1 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************