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* Detailed Description:
* Purpose of the example is to show how to maintain SRAM data over reset types
* that is not destroying SRAM content (for instance software reset)
* Changes are done in linker command files (adding new section), because
* .BSS and .SBSS section are always cleared by compiler.
* Another changes are done in init.s file where SIU_RSR reset flags are
* tested and RAM is initialized only conditionally.
* Variable 'test_variable' is maintained over SW reset and then incremented
* once per reset cycle and displayed over terminal window.
*
* ------------------------------------------------------------------------------
* Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C
* MCU: PPC5777CMM03 2N45H CTZZS1521A
* Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz
* Debugger: Lauterbach Trace32
* Target: internal_FLASH
* Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A
* EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1)
* ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2)
*
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