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* Detailed Description:
* This example demonstrates basic functionality of SARADC (10-bit ADC0 and 12-bit ADC1) in one-shot conversion mode.
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* Test HW: MPC57xx
* Maskset: 1N81M
* Target : SRAM
* Fsys: 160 MHz PLL
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Revision History:
1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version
1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0
1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup
1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL
1.4 Mar-10-2016 b21190(Vlna Peter) Added ADC driver
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