Example MPC5744P 1b+2b_FLASH_ECC_error_by_UTEST_area_read GHS614

[#1]

********************************************************************************
* Detailed Description:
* Purpose of the example is to show how to generate Multi-bit or Single-bit ECC
* error in internal FLASH (user must choose it in the option at the end of main
* function).
* ECC error is injected by reading of pre-defined patterns in UTEST area at
* addresses 0x00400040 and 0x00400060.
* When corrupted data is accessed the IVOR1 exception handler is called in case
* of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt
* handler is called in case of single-bit ECC error (FCCU interrupt occurs).
* Both function calls MEMU handler.
* The example displays notices in the terminal window (connector J19 on
* MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A).
* No other external connection is required.
* ------------------------------------------------------------------------------
* Test HW:         MPC57xx_Motherboard + MPC5744P-144DC
* MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B
* Fsys:            200 MHz PLL with 40 MHz crystal reference
* Debugger:        Lauterbach Trace32
* Target:          internal_FLASH, RAM
* Terminal:        19200-8-no parity-1 stop bit-no flow control
* EVB connection:  default
********************************************************************************

[ahmedsoubky]

Hi David, 

I have a question regarding the code. 

Is it possible to disable the machine check interrupt and only generate FCCU alarm interrupt when we read from 2-bit ECC error address ? 

Thanks in advance, 
Best Regards,

Ahmad

[davidtosenovjan]

No, it is not possible. In case code flash (data or instruction) reading of location with double bit ECC error by the core leads in exception. No data is returned. Exception handler must manage this erroneous condition.

In case double bit ECC error in eeprom flash MPC5744P returns 0xFFFF_FFFF and it can by managed SW way without program flow interruption.