Some follow-up context and questions:
My goal in using the Deep Sleep mode is to stop all internal clocks, and wake on a UART Rx Edge. (I will actually need to wake from any of the LPUART Rx signals: LPUART0, LPUART1, and LPUART2). Ideally, the wake delay would be short enough that the UART could service the incoming byte that caused the wake up.
I was able to "wake" on the Rx Edge during debugging with DBGCTL[SOD] = 0 (enable debug during sleep). However, without the debugger attached, the Rx Edge failed to wake the chip. I now realize that the Rx Edge was likely only detected because the core clock remained enabled by the SOD setting.
So, a possibly dumb question: In order to serve as a wake-up source, is it necessary for a module to remain clocked? If so, then it seems I will not be able to achieve my goal of silencing all clocks.
From the Reference Manual, 23.3.3 Deep Sleep mode (pg 670):
Some modules can remain operational with low power asynchronous clock sources and serve as wake-up sources.
So it seems I either need to clock the WUU and use it to wake the unit. (In that case, I don't think a UART Rx edge can be used, as none of the LPUART signals are listed in Table 84, Wakeup Source for WUU inputs). Alternatively, I need to clock a module itself (e.g. clock the LPUART either from an asynchronous clock source or the LPO CLK16K0) if I wish to use it as a wake-up source during low power operation. Is this accurate?