UART Setup on FRDM-MCXN947

[John_Adams]

Hello,
I'm trying to reset LPUART to the frequency from FRO_HF (48 MHz) and keep baudrate 230400. Unfortunately I can't get it to work despite setting the CLK for the UART and baudrate. Have I forgotten something? Can I somehow change the divider?

    /* attach FRO HS to FLEXCOMM7 */
    CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 1u);
    CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM7);

My LPUART setup:

    LPUART_GetDefaultConfig(&config);
    config.baudRate_Bps = 230400;
    config.isMsb        = false;
    config.enableTx     = false;
    config.enableRx     = true;

    PRINTF("Frequency: %d\r\n", CLOCK_GetLPFlexCommClkFreq(7u));
    freq = CLOCK_GetLPFlexCommClkFreq(7u);
    LPUART_Init(LPUART7, &config, freq);
    uint32_t divider = ((LPUART7->BAUD & LPUART_BAUD_SBR_MASK) >> LPUART_BAUD_SBR_SHIFT);

    DisableIRQ(LPUART7_IRQn);
    /* Enable RX interrupt. */
    LPUART_EnableInterrupts(LPUART7, kLPUART_TransmissionCompleteInterruptEnable);
    EnableIRQ(LPUART7_IRQn);

Thank you

John Adams

[EdwinHz]

Hi @John_Adams,

Please make sure you are also initializing the appropriate pins on the pin_mux.c file under board folder.

BR,
Edwin.

[John_Adams]

Thank you for your answer @EdwinHz 
I have the pins installed, I don't have a problem that LPUART doesn't work at all, I have a problem that UART doesn't keep up with the speed of communication on FRO_12M. I am trying to increase the frequency, but I have the feeling that the baudrate is not set correctly, how can I change the divider?

John Adams

[EdwinHz]

Hi @John_Adams,

You can chance the FC7 divider by using the line you previously mentioned:

CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 1u);

 However, this is already at the lowest division possible. increasing the divider will only decrease the frequency. If you wish to increase the FC7 frequency, you can try changing the source clock to another source, like the PLL divided clock (pll_clk_div) using:

CLOCK_AttachClk(kPLL_DIV_to_FLEXCOMM7);

Just make sure you are enabling this PLL divided clock by using:

CLOCK_AttachClk(kPLL0_to_PLLCLKDIV);
CLOCK_SetClkDiv(kCLOCK_DivPllClk, 1U);

BR,
Edwin.

[John_Adams]

Thank you,
Also I will have to use LPUART FIFO, can you please advise me how to read sequentially the data from this FIFO queue?

John Adams

[EdwinHz]

Hi @John_Adams,

You could sequentially read the FIFO queue by letting the eDMA automatically handle these reads. Please look at the "lpuart_edma_transfer" example code, as it shows how the eDMA handles the FIFO reads automatically.

BR,
Edwin.

[John_Adams]

Thank you Edwin,
I will look at the example. Just by chance, is there any example that would use FIFO and not use EDMA?

John Adams

[EdwinHz · Accepted solution]

Hi @John_Adams,

Of course, that would be any of the other LPUART examples that we provide in our SDK:

BR,
Edwin.