Trying to make I2S work on FRDM-MCXC444

[Qual]

Hi, I'm trying to make I2S work on FRDM-MCXC444 through configuring it with MCUXpresso Config Tools, but I've encountered a couple of problems:

1. Using DMA with callback, there is some empty buffer sent before callback is called.

(top - BCLK; middle - WSCLK; bottom - data(32 packages filled with ones). Callback repeats the same transaction using the same buffer. Expected behavior - WSCLK is 1 after transaction is over, much smaller delay before callback)

2. Setting the target frequencies does not work.

Encountered scenarios:

MCLK is fed from System clock(12MHz), target frequency set to 3.072 MHz(Config Tools says this frequency will be created using fractional frequency divider).

BCLK is set to replicate MCLK, 3.072MHz to meet sampling frequency of 48kHz with word width 32 bits.

This configuration produces this result:

(BCLK ~23.437kHz)

(MCLK ~3.989MHz)

I couldn't find any explanation for given behavior apart from speculation around "overloading" the fractional divider with such precise target frequency. Still, configuration tool doesn't inform about anything happening with clocks.

[Celeste_Liu]

Hello @Qual ,

Thanks for your post. Based on the problems you described, I think it is largely due to incorrect MCLK configuration.

About the I2S interface, the configurations of MCLK and BCLK are depend on the design specs of the CODEC chip used.

Typically, MCLK is set as an integer multiple of the sampling frequency (fs), such as 64fs, 128fs, or 256fs. Its primary purpose is to ensure the precise synchronization between the transmitting and receiving ends and, in certain cases, to supply the necessary working clock for the CODEC.

The BCLK is configured as 3.072 MHz, which is in accordance with the sampling frequency of 48 kHz and a word width of 32 bits, and this configuration appears to be correct.

In practical applications, MCLK is commonly configured to be an integer multiple of BCLK. If you opt for a 256fs relationship between MCLK and the sampling frequency, then MCLK would be 48000Hz * 256 = 12.288MHz. This integer multiple relationship is crucial for guaranteeing a stable clock distribution to the CODEC.

Consequently, the configuration of MCLK is determined by the CODEC in use. It is important to refer to the CODEC's datasheet when setting up these clocks to ascertain the appropriate values. I am currently unaware of the specific CODEC model you are employing. If possible, could you kindly provide me with this information?

Besides, is your MCXC444 functioning as a master or a slave?

As for the situation you mentioned that no prompt information appears when using the MCUXpresso Config Tools for configuration, even if the configuration is unreasonable, it is indeed possible to occur in actual operation. Because when configuring I2S, the relevant parameters are mainly determined by the CODEC, not our MCU. Therefore, from this perspective, the situation where no prompt appears also has a certain degree of rationality.

Hope it can help you.

BRs,

Celeste

[Qual]

I'm sorry for not providing more information in my post.

I'm using MCXC444 as master to send information to external DAC(PCM5102A), which supports different clock frequencies and generating MCLK on it's own, what allows me to use 3-wire connection. I'm targeting setup with fs=48kHz, BCLK=3.072MHz and word width of 32 bits. Because of this setup, the MCLK is used only to feed the BCLK.

The project I'm testing with is attached to this reply.

Here are results captured by my logic analyzer:

MCLK:

BCLK:

FS and TX:

Screenshots are separated because simultaneous connection resulted in jittering and very inconsistent waveforms. I'm not sure if this is a product of my logic analyzer or MCU. Still, the captured frequencies do not match one's configured through config tool.

Results are better when BCLK is generated not by MCLK, but through other clock and prescaler. Sadly, this arrangement doesn't allow to match needed frequency with enough precision.

Best Regards,

Qual

[Celeste_Liu]

Hello again @Qual ,

Sorry for taking a while to get back to you. I truly appreciate your providing me with more detailed information. Referring to your Mex configuration, I have also conducted some tests. Since I don't have the PCM5102A module on my side, I could only briefly examine the waveform of I2S. As shown in the figure below, I deem it to be okay. Note that from top to bottom are BCLK, FS, TXD, and MCLK in sequence.

I have reviewed your code and Mex configuration. In my opinion, there is an issue with the selection of MCLK. You stated that MCLK is sourced from the external DAC (PCM5102A). Therefore, according to "5.7.10 I2S/SAI clocking" in the RM, the MCLK Source should be set as MCLK_in instead of the System Clock.

About more configurations regarding the I2S master, you can refer to "39.5.6 I2S Master" in the RM.

Hope below message can help you.

BRs,

Celeste