Hello @dhruvinrajpura
For i.MX8ULP, the current BSP doesn't provide tool to change the cpu frequency, if we need to change the frequency, we can modify register value by using /unit-tests/memtool.
According to RM, from Chapter Clocking, we can know PLL2 is used exclusively for the A35, and in Chapter Clock Generation and Control(CGC1), there is a group of PLL2 registers, among them,
there is a division unit and a multiplication unit:
Overall, we can follow such steps to change the A core frequency:
- Switch a35 to another reference clock
- Modify PLLEN to 0
- Modify multiplication and division factors
- Modify PLLEN to 1
- Switch 35 back to PLL2
# Switch a35 to FRO 192 MHz
/unit_tests/memtool -32 0x292c0014=0x08000000
# Set PLLEN to 0
/unit_tests/memtool -32 0x292c0500=0x03000000
# Read and set the division and multiplication factors
/unit_tests/memtool -32 0x292c0014 1
/unit_tests/memtool -32 0x292c0510 1
# Set PLLEN to 1"
/unit_tests/memtool -32 0x292c0500=0x03000001
# Switch a35 to PLL2"
/unit_tests/memtool -32 0x292c0014=0x18000000
mhz
About of question 2, you can see the low_power_display.c example in the i.MX8ULP SDK:
boards\evkmimx8ulp\demo_apps\low_power_display
it demonstrates how to use CM33 core to do a triple buffer pan display with total i.MX8ULP SoC power around 90mW. In this demo, the display controller, MIPI DSI host is controlled by CM33 instead of Application Domain (A35 cores). The frame buffers are put into the external PSRAM through FlexSPI interfaces, this can keep the DDR in retention mode to save power. The display content refresh rate is limited to one fps, RTD domain will enter sleep mode to save power after updated the display buffer address every seconds.
Best regards,
Salas.
