Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI

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Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI

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jyothz
Contributor II

Hi Team,

We are currently working on interfacing the i.MX RT1170-EVKB board with a camera using a 2-lane MIPI interface. In our setup, all camera control signals are managed by an FPGA, while the i.MX RT1170 board is responsible only for receiving image data from the FPGA and streaming it to the host system.

We have attempted to modify the “uvc_rgb_imxrt1170” example project by bypassing the camera initialization and I²C control sequences, since the camera is managed externally. However, we have not yet been able to verify whether the board is successfully receiving data over the MIPI interface.

The camera specifications are as follows:

  • Pixel format: 12-bit monochrome

  • Resolution: 2048 × 2048

  • Data source: FPGA (via 2-lane MIPI)

Before proceeding further, we would like clarification on the following points:

  1. Is it feasible to interface the i.MX RT1170-EVKB with an FPGA-based MIPI source by replacing the OV5640 camera?

  2. Can the existing PXP (Pixel Pipeline) module handle the 12-bit monochrome data format described above?

For reference, we have attached details of the MIPI connector used and the example project originally designed for streaming data from the OV5640 camera.

 

jyothz_0-1759986908362.png

FPGA to IMXRT1170 connector (J2 in IMX BOARD)

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Any information regarding this will be much valuable and helpful.


Thank you for your guidance and support.
Jyothish

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Sam_Gao
NXP Employee
NXP Employee

Hi,

It is feasible to interface the i.MX RT1170-EVKB with an FPGA-based MIPI source, but the PXP module will require data format conversion to handle 12-bit monochrome data.

  • Q1. FPGA-based MIPI Source Interface: Interfacing an FPGA that acts as a MIPI CSI-2 camera source is possible. The i.MX RT1170-EVKB is equipped with a MIPI Camera Module Connector (J2) designed for this purpose. But we don't have such solution to support by using FPGA-based MIPI source.
  • Q2. PXP and 12-bit Monochrome Data: The PXP (Pixel Pipeline) is a 2D graphics accelerator capable of operations like color space conversion, rotation, and resizing , . However, it does not have native support for a 12-bit monochrome (grayscale) input format.
    • Supported PXP Formats : The PXP supports a variety of RGB and YUV formats, including 8-bit monochrome ( Y8 ) and 4-bit monochrome ( Y4 ),. There is no documented support for a 12-bit monochrome ( Y12 ) input.
    • Required Workaround : To process the image with the PXP, the 12-bit monochrome data must be converted into a supported format before it is passed to the PXP. 

 

 

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jyothz
Contributor II

Apologies for the delayed response, and thank you for your valuable input earlier — it helped us confirm that the setup is indeed feasible.

We have an additional query: In our setup, an FPGA is connected to a camera module and continuously streams image data to the i.MX RT1170 controller via the MIPI interface. Since the FPGA handles all communication with the camera, we have excluded the I2C-based camera initialization from the i.MX RT1170 side.
Our question is: Will the MIPI interface on the i.MX RT1170 still function correctly if we completely remove the I2C camera initialization sequence, considering that the FPGA does not require any I2C interaction? Or, are there any I2C-dependent flags, registers, or status bits within the i.MX RT1170 MIPI subsystem that are mandatory for proper MIPI operation?

Thank you for your time and guidance.

Best regards,
Jyothish

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