How to understand General purpose IO structure diagram and pad control register?
Here are relative pictures below.
Why does ODE take the opposite, then perform "&" operations with Pull_Keeper_Enable, and then take the opposite of the computed result? In the description of register, Pull_Keeper_enable when Pull_Keeper_Enable == 1. So the diagram are different from the description of register.
What is the meaning of pull_en_b?
Why is there no Pull_Enable to work in the diagram?
In input mode, why are two inverters connected in series, and how can they take effect? Is their function to latch input data or to act as a delay circuit?
