Hi Carlos,
Thanks for the quick response.
Since the timing is very tight, each clock pulse is 1 µs (500 ns ON and 500 ns OFF). I initially tried using an ISR, but the ISR latency itself takes longer than the pulse period, which causes the pulse to become distorted. The board clock runs at 96 MHz, so each MCU clock cycle is about 10.41 ns. Even a single instruction or conditional check introduces enough delay to further distort the pulse.
I tested using a CTimer match with the pin mapped directly, and that works; however, it does not allow control of all the GPIOs that need to be driven. I then tried using CTimer with DMA to control the GPIOs, which does work.
However, when the matchValue is set to 48, the DMA interrupt occurs later than 500 ns. When the matchValue is set to 7, the timing is closer to the expected 490/510/500 ns range. I am not sure why the CTimer is not triggering the interrupt at the exact expected time when DMA is linked.
I am attaching the code for reference. Do you have any ideas or suggestions other than this approach? Please let me know.
Thanks.