Hello @Crshi ,
Thanks for your post.
According to the description of RM, "When the ewm_out_b signal asserts, an interrupt request can be generated to indicate the assertion of the EWM reset out signal. The interrupt is enabled when CTRL[INTEN] = 1. Writing 0 to this field clears the interrupt request but does not affect the ewm_out_b signal, which can be deasserted only by forcing a system reset."
Therefore the ewm_out_b signal determines whether an interrupt request will be generated, while INTEN bit determines whether the interrupt is allowed to be passed to the CPU. In other words, when ewm_out_b is asserted and INTEN = 1, the interrupt request will be sent to the CPU, but whether the IRQ handler is ultimately executed depends on the following additional conditions:
1. The interrupt is not masked by a higher-priority interrupt;
2. The interrupt vector table is correctly configured;
3. The NVIC has enabled the EWM0 interrupt.
The interrupt number of EWM can be found in "Table 15. Interrupt Vector Assignments" of the RM.

Hope it can help you.
BRs,
Celeste
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