Does SS clear MCU SPI FSM/shift counters in slave mode

[asdf_gone]

Hi all, I am wondering if setting SS high while SPI slv in these MCUs (MC9S12ZVMRM, MC68HC908GZ60) returning a read data would reset the SPI slv logics such as FSM and shift, so the next transaction could function correctly. 

In MC9S12ZVMRM, it didn't list that as an error case, but in MC68HC908GZ60, it treats that as an erronous situation, but the manual didn't quite explain what would happen to the SPI slv logics. 

My assumption is that SPI slv generally would reset its logics after CS is high, but I would like to make sure with yall. 

[lama]

Hi,

Yes SS resets the status of the slave.

Best regards, Ladislav

[asdf_gone]

The status includes the shift register counter for the slave output, right? I know it is a bit silly to ask, but have you guys tested this error case？

[lama]

Hi,

yes there is a counter. The peripheral structure is an IP block and should be used as black box. Of course, the number of pulses must be calculated and action must be done if there is an issue.

Best regards,

Ladislav

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Any help would be greatly appreciated, thanks