I have to read data from a serial Nor flash, connected to my RT1xxx through LPSPIx.
I have to send one command byte and then I have to read 10KB data.
It would be nice to do this with two transfers:
- a 5-byte transfer in tx, composed by
1 command byte
3 address byte
1 dummy byte - another transfer with 10KB rx buffer, and NULL tx buffer
obviously the chip-select must be asserted at the first transfer and de-asserted at the end of the second transfer, between the two transfers the chip-select must remain asserted. In other words CONT must be 1 and CONTC 0 in the first transfer. While in the second transfer both CONT and CONTC must be 1. At the end of the second transfer CONTC shoud be written 0 to deassert CS. Obviously only one TCR write must be made between the two transactions.
I tried to draw a time diagram to explain myself better:
In the first transaction I only write, in the second transaction I only read, but between the two the PCS must remain asserted.
I am using SDK 2.15.000, how can I achieve this behavior using API of SDK?
You may ask why do I need this? A single call to LPSPI_MasterTransferBlocking() would force me to allocate both rxData and txData buffers with two vectors of more than 10KB, in which the tx buffer is completely useless. Is exactly what I would like to avoid.
Note that some years ago I asked the same question, but did not get a satisfactory answer.
best regards
Max
