Setting i2c/SPI baud rate on rt1050?

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Setting i2c/SPI baud rate on rt1050?

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jackking
Senior Contributor I

I'm trying to set my i2c bus to run at 1MHz, but it seems to be running at 200kHz max.

I am using the rt1050 EVK and the following to set the clock (based on the SDK example):

/* Select USB1 PLL (480 MHz) as master lpi2c clock source */
#define LPI2C_CLOCK_SOURCE_SELECT (0U)
/* Clock divider for master lpi2c clock source */
#define LPI2C_CLOCK_SOURCE_DIVIDER (1U)
/* Get frequency of lpi2c clock */
#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U))

 

#define LPI2C_MASTER_CLOCK_FREQUENCY LPI2C_CLOCK_FREQUENCY

 

#define I2C_BAUDRATE 1000000U

...

LPI2C_MasterGetDefaultConfig(&masterConfig);
 /* Change the default baudrate configuration */
 masterConfig.baudRate_Hz = I2C_BAUDRATE;
 LPI2C_MasterInit(EXAMPLE_LPI2C_MASTER_BASEADDR, &masterConfig, LPI2C_MASTER_CLOCK_FREQUENCY);‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Am I doing something incorrectly?

Thanks

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CarlosCasillas
NXP Employee
NXP Employee

Hi Jack,

You could take a look to the i.MX RT Clock tree on figures 18-2 and 18-3 of the i.MXRT1050 Reference Manual:

https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf


Hope this will be useful for you.
Best regards!
/Carlos

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jackking
Senior Contributor I

Carlos,

The reference manual is what I have been using already.

Specifically Figure 18-2.

This diagram shows Usb1PllPfd0Clk should be 720 MHz, in my case it maxes at 432MHz with:

CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 1);

Then the LPSPI clock select (kCLOCK_LpspiMux) chooses the clock source, and the clock divider (kCLOCK_LpspiDiv) feeds the baudrate calculation. Set with:

/* Select USB1 PLL PFD0 (720 MHz) as lpspi clock source */
#define EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT (1U)
/* Clock divider for master lpspi clock source */
#define EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER (0U)

CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_SetMux(kCLOCK_LpspiMux, EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_LpspiDiv, EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER);
CLOCK_EnableClock(kCLOCK_Lpspi3);

Even then, the optimum baudrate calculation is not actually manifested in the SCK signal being generated.

Set with LPSPI_MasterSetBaudRate during the LPSPI init.

IMXRT1050RM_pdf__page_680_of_3_569_.png

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jackking
Senior Contributor I

I also tried running one of the SDK samples *unchanged*, it is supposed run at 500kHz baud, but it only clocks at 333kHz.  So either I am misunderstanding the measurement/baudrate, or the SDK sample is also not running at the correct clock on the rt1050.

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jackking
Senior Contributor I

OK, in case anyone else runs into the same trap, I think I have discovered what my issue is... 

Looking at the MCUXpresso Clock Config Tool, for any new project, PLL3_PFD0 is *not* defaulted to 720MHz, it is set to 261.81MHz. 

You can change this in the config tool to get 720MHz.

You can also specify the LPSPI functional clock source and divider in the Clock Config Tool, which is updated and set in clock_config.c.

I'm not sure why the SDK samples do this in the main code.

I was trying to set the SPI clock source and divider in my main code and assuming PLL3_PFD0 was defaulting to 720MHz on reset as specified in the Reference Manual, I was unaware that clock_config.c was also setting PLL3_PFD0 and the LPSPI clock, so they were conflicting with each other.

So... the end result, I would recommend using the clock config tool in favor of manual config in code, and validate the values in the config tool are what you expect, not assuming they are the defaults!

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jackking
Senior Contributor I

I traced the PLL3 config for the SDK sample, and it seems that it is bypassed, passing the 24MHz system clock instead of the 480MHz clock configured in the Clocks Config tool.

CLOCK_IsPllBypassed() for PLL3 always returns true, regardless of the setting in the Clock Config tool.

There is a comment in clock_config.c that seems to indicate that using the rt1050 with XIP uses PLL3 and blocks the configuration of PLL3 by the Clock Config tool?

Here is the comment:

    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/

This would explain why the clock for PFD0 is showing as 36MHz instead of the expected 720MHz when setting the PFD0 scale, and higher baudrates are not achievable on LPSPI using PLL3_PFD0...

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jackking
Senior Contributor I

I still have had no luck getting SPI above 12MHz, even when it looks like it should be running at 27MHz based on the baudrate selected from a requested 36MHz rate.  I must be missing something that is limiting the SCK.

Here are the relevant settings I am using:

/* Select USB1 PLL PFD0 (720 MHz) as lpspi clock source */
#define EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT (1U)
/* Clock divider for master lpspi clock source */
#define EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER (0U)
#define EXAMPLE_LPSPI_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER + 1U))

#define EXAMPLE_LPSPI_MASTER_CLOCK_FREQ EXAMPLE_LPSPI_CLOCK_FREQ
#define EXAMPLE_LPSPI_MASTER_BASEADDR (LPSPI3)
#define TRANSFER_BAUDRATE (36000000U)

PRINTF("clk: %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));

/*Set clock source for LPSPI*/
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 8);
PRINTF("aclk: %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
PRINTF("aspi: %d\n",(CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)/ (EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER + 1U)));

CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_SetMux(kCLOCK_LpspiMux, EXAMPLE_LPSPI_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_LpspiDiv, EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER);
CLOCK_EnableClock(kCLOCK_Lpspi3);

/*Master config*/
    masterConfig.baudRate = TRANSFER_BAUDRATE;
    masterConfig.bitsPerFrame = 9;
    masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
    masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
    masterConfig.direction = kLPSPI_MsbFirst;

    masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
    masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
    masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;

    masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;
    masterConfig.pcsActiveHighOrLow = kLPSPI_PcsActiveLow;

    masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
    masterConfig.dataOutConfig = kLpspiDataOutRetained;

    LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, EXAMPLE_LPSPI_MASTER_CLOCK_FREQ);

This outputs:

clk: 36000000
aclk: 54000000
aspi: 54000000
best LPSPI PRESCALE: 0
best LPSPI SCKDIV: 0
best LPSPI baudrate: 27000000

Looking at the actual SCK on the scope, it maxes out at 12MHz:

DS1Z_QuickPrint2.png

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jackking
Senior Contributor I

Now I also have a similar question regarding setting the SPI baudrate. 

The max I can get is 5MHz on SPI, using the sample code for lpspi.

When I check the USB clock frequency using:

PRINTF("clk: %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));

I get:

clk: 36000000

Not the commented value of 720 MHz in the sample...

Ideas?

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