RT1064 internal flash

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RT1064 internal flash

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biafra
Senior Contributor I

Hi eveyone,

 

I have a custom board with RT1064, using MCUXpresso 11.5.0 and SDK 2.11.0.

I'm trying to use internal flash to store some configuration and setting data. I've read this post: https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/How-to-use-the-RT1064-on-chip-flash-as-NVM/ta-p/..., that covers the modifications to do to adapt the SDK examples (external IS25W memory) to the internal memory (W25Q32JV memory).

There are a couple of doubts I have:

  • As stated in the datasheet, to enable the quad mode in the W25Q32JV we must set the bit 1 (mask 0x02) in the status register 2 with command 0x31 instead setting the bit 6 (mask 0x40) in the status register with command 0x01. So I think there is the need to define a new command item in the customLUT array and to modify the flexspi_nor_enable_quad_mode() function:

 

 

#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG2    14
/* Enable Quad mode */
[ 4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG2 ] =
    FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x31, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04 ),
status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base)
{
    ...
    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG2;
    ...
}

 

 

  • I don't understand the need to exchange the FLEXSPI command index for NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD and NOR_CMD_LUT_SEQ_IDX_READ_NORMAL to align with XIP settings: the modified code is compiled exactly the same way as the original one

 

Are these considerations corret?

 

Many thanks

Biafra

 

1 Reply

850 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi @biafra ,

1. The EQ bit is NVM. So, user only need to program it one time. Other project needn't write it again and again.

2. Yes, you are right. FlexSPI and FlexSPI2 are different instance. They needn't align with XIP settings.

 

Regards,

Jing