Need Help: LS1046ARDB - DMA Bus Error in IM Ethernet driver

[srak]

I am using a custom RTOS and to use Ethernet, I have ported the uboot FMAN driver. It seems the porting is successful (Microcode download, Rx/Tx port, PHY, memac initialization) but Tx and Rx is not working.

I am getting DMA Bus error during Tx. The following are the values in FMAN DMA register when error occurs.

FMDM_SR = 0x00000018 --> Command Queue not empty and Bus error event
FMDM_MR = 0x00E80030
FMDM_TR = 0x003F003F
FMDM_SETR = 0x00000000
FMDM_HY = 0x0000002A
FMDM_TAH = 0xDE000000
FMDM_TAL = 0xDEADBEEF --> What this error means? Buffer overflow? Invalid access?
FMDM_TCID = 0x0000002A --> EMAC3 Tx port Id is correctly set (0x2A)

The memory for Tx Desc is allocated from SDRAM (0x81108000). Instead, if I allocate from FMAN memory (0x01A03000) then DMA bus error not occurring and Tx as well as Rx is working. I don't understand why I get DMA bus error when use SDRAM.

What could be the reason for such an error? What register setting should I check? Thanks in advance for your help.

[srak · Accepted solution]

The issue was solved by disabling cache for Buffer and Buffer Descriptor used in Ethernet driver (used in Parameter RAM). In custom RTOS, cache was enabled by default for whole SDRAM.

[srak]

FMDM_TAL holds the lower 32 bits of the address accessed during the current bus transaction. In case of
a bus error or watch-point event, the address is captured in the register until the corresponding status bit in
the FMDM_SR register is reset.

Yes, I read it in document. When error occur, I expect to see some address in FMDM_TAL value, but the value I see is 0xDEADBEEF which is not an address. Could it mean out of range access?

It looks like a Configuration Register Access error.

Any permission/security/mmu settings need to be enabled specific for FMAN DMA? 

In document, '5.12.15.6 IM Application Notes', it says the MR[3] in FMBM_TFCA/FMBM_RFCA should be set to 1 for external memory accesses in extended mode. I have done this. Any other value needs to be to set in MR? In document no information about possible values of MR.

[Oswalag]

It is correct, user must initialize MR[3] to 1. This assures extended address mode for external memory accesses.

FMDM_SR

BER Reset the Ber bit writing 1 before unmasking

*****FMDM_MR

BMI_EMR It is recommended to clear this bit

ECC_MSK 0 Mask ECC error events (if needed)

*****FMDM_TR, FMDM_HY, FMDM_SETR  are correct

FMDM_TAH and FMDM_TAL in both to avoid errors like the DEADBEEF that means an error in the register Reset the Ber bit writing 1 before unmasking.

you said "The memory for Tx Desc is allocated from SDRAM (0x81108000)" why did you select this memory space?

[srak]

you said "The memory for Tx Desc is allocated from SDRAM (0x81108000)" why did you select this memory space?

I ported the code from u-boot and u-boot is using SDRAM space (memory for BD and Buffer are allocated by malloc()).

Ref: fm_eth_tx_port_parameter_init()

https://github.com/ARM-software/u-boot/blob/master/drivers/net/fm/eth.c 

[Oswalag]

I understand, you can review the LSDK 21.08 user guide to see as a example the Linux implementation of the driver for the Frame Manager to compare the configuration with your custom RTOS, in LSDK it is tested and works fine with the LS 1046ARDB.

[srak]

Sure, will check it. Between, the custom RTOS uses Aarch32 mode. The Linux and u-boot runs in Aarch64 mode. Using Aarch32 mode could cause such problem?

[Oswalag]

Yes, for AArch32 support, the specific U-Boot and Kernel images are used and you can find them in the QorIQ SDK v2.0-1703 Documentation.

[srak]

I see, so it means the IM driver should work in Aarch32 as well. I will give a try. Thanks!!

[Oswalag]

Hello,

It looks like a Configuration Register Access error.

FMDM_TAL holds the lower 32 bits of the address accessed during the current bus transaction. In case of
a bus error or watch-point event, the address is captured in the register until the corresponding status bit in
the FMDM_SR register is reset.

Please take a look of the DPAA Reference Manual to see the requirements to avoid any issue in the following link:

https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/la...