Hi,
Yoy are right, if you configure the pin P2.00 pin, you have to configure the PINMODE4[1:0] as the value in the pic.
If you set the PINMODE4[1:0]=11 in binary, the p2.00 will be low by the on-chip weak pull-down resistor.
If you want to set/clear the P2.00 pin, you can configure the P2.00 in GPIO output mode and set or clear the pin.
This the configuration of P2.00 in GPIO output mode.
PINSEL4[1:0]=00 in binary; the pin function as GPIO
FIO2DIR[0]=1 in binary, //p2.00 direction register bit is 1, output mode
FIO2SET[0]=1; set the P2.00 pin
FIO2CLR[0]=1; clear the P2.00 pin
Hope it can help you
BR
XiangJun Rong
Hi,
For the LPC1768, the ISP pin is P2.10 instead of P2.0. After the Reset, the boot code in ROM is executed, the pin P2.10 is sampled to decide if the chip enters ISP mode or application code, if the P2.10 is sampled LOW, the application code is executed, if the P2.10 is sampled high, the chip enters ISP mode.
After Reset, the bits21/20 in PINMODE4 register are 00, the on-chip pull-up resistor is enabled in default, the P2.10 pin is in high logic in default after Reset, the application code is executed.
Because the P2.10 is sampled after Reset before any application code is executed, it is IMPOSSIBLE to configure the PINMODE4[20:21] bits to zero in application code so that the chip can enter ISP mode. it is the only way to connect a pull-down resistor on the P2.10 pin in order to enter ISP mode. This is a common practice to connect P2.10 pin to a hardware button so that you can control the logic after Reset.
Hope it can help you
BR
XiangJun Rong
32.3 Description
The flash boot loader code is executed every time the part is powered on or reset. The
loader can execute the ISP command handler or the user application code. A LOW level
after reset at pin P2.10 is considered an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when the
rising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled
and the decision on whether to continue with user code or ISP handler is made. If P2.10 is
sampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program.
If a valid user program is found then the execution control is transferred to it. If a valid user
program is not found, the auto-baud routine is invoked.
Pin P2.10 is used as a hardware request signal for ISP and therefore requires special
attention. Since P2.10 is in high impedance mode after reset, it is important that the user
provides external hardware (a pull-up resistor or other device) to put the pin in a defined
state. Otherwise unintended entry into ISP mode may occur.
When ISP mode is entered after a power on reset, the IRC and PLL are used to generate
the CCLK of 14.748 MHz. The baud rates that can easily be obtained in this case are:
9600 baud, 19200 baud, 38400 baud, 57600 baud, 115200 baud, and 230400 baud. This
may not be the case when ISP is invoked by the user application
