How to run the SDK sample lwip_dhcp_freertos on SDRAM?

[atm2024]

Hi everyone,

I am using MIMXRT1064-EVK with SDK version 2.15.0.
I am trying to run the SDK sample lwip_dhcp_freertos on SDRAM.

I added the below symbols to the project.
> SKIP_SYSCLK_INIT
> XIP_BOOT_HEADER_DCD_ENABLE=1

Next I moved BOARD_SDRAM to the top of memory details.
> RAM BOARD_SDRAM RAM 0x80000000 0x1e00000
> Flash PROGRAM_FLASH Flash 0x70000000 0x400000 MIMXRT1064.cfx
> RAM SRAM_DTC RAM2 0x20000000 0x20000
> RAM SRAM_ITC RAM3 0x0 0x20000
> RAM SRAM_OC RAM4 0x20200000 0xc0000
> RAM NCACHE_REGION RAM5 0x81e00000 0x200000

and checked Link application to RAM.

When I build and run the project, it works as expected at first.
However, even if you repeatedly connect and disconnect the LAN cable after that, the DHCP state does not change.

How can I run it on SDRAM?

Thanks in advance.

[atm2024]

I'm continuing to investigate this issue, but the issue has not been resolved.
What I want to know is, is it okay to put variables in SDRAM when using lwip in my project?

At least, in the SDK sample lwip_dhcp_freertos, if you set "Global data placement" to NCACHE_REGION of SDRAM, ethernet link detection does not work properly.
GPIO1_Combined_0_15_IRQHandler() is being called frequently due to factors other than PHY interrupts, and it is likely that the state in which the PHY interrupts of GPIO1-10pins are Low is being missed.
I don't know why GPIO1_Combined_0_15_IRQHandler() is called frequently when setting "Global data placement" = NCACHE_REGION.
In the case of "Global data placement" = SRAM_DTC, SRAM_OC, and BOARD_SDRAM, the frequency of calls is obviously low. And that's normal.
Is this due to the difference in processing speed between cacheable and non-cacheble?

Thanks in advance.

[atm2024]

After all, it seems better not to place Ethernet resources in SDRAM (BOARD_SDRAM, NCACHE_REGION).
I don't know why. However, something similar happened in the post below.

https://community.nxp.com/t5/i-MX-Processors/TCP-Ethernet-Lwip-No-issue-with-SRAM-DRAM-but-issue-wit...

https://community.nxp.com/t5/i-MX-Processors/iMXRT1024-Ethernet-MAC-not-transmitting-data/m-p/178237...

I have no choice but to use SRAM.

By the way, the symptom when using SDRAM is that for some reason phy_irq_synced_handler() is called many times during TCP communication. Also, GPIO1_Combined_0_15_IRQHandler() is called frequently.
Both of these points are strange behavior.
This behavior does not occur when using SRAM.

In the future, I hope this will be improved so that it will work properly even if the Ethernet resources are placed in SDRAM in order to run large applications.

[atm2024 · Accepted solution]

I found the cause.
The ENET_INT pin on the MIMXRT1064-EVK board is pulled up (R309) and down (R152).
In this state, the GPIO1_Combined_0_15_IRQHandler() interrupt will occur at irregular intervals even if nothing is being done.
If you remove R152, the sporadic GPIO1_Combined_0_15_IRQHandler() interrupts will no longer occur.
And the GPIO1_Combined_0_15_IRQHandler() interrupt will only be raised if the Ethernet link is up or down.

[atm2024]

Hi, Omar.

Thank you for answering.

I understand that both SRAM_DTC and NCACHE_REGION are not cached.

I don't think it will affect the operation of the program other than speed, is that correct?

If so, I think the program will work properly even if the Heap region or NonCacheable region is allocated to NCACHE_REGION on SDRAM.

However, the operational results were different.

I want to know the reason.

Thanks for your cooperation.

[Omar_Anguiano]

This is because when cache used on some critical parts data coherency cannot be maintained so we need to secure to other methods as mentioned in the document you found. 

Best regards,
Omar

[atm2024]

I think I understand the role of cacheable and non-cacheable.

But I can't understand why something like the following happens.

In the lwip_dhcp_freertos project,

it works fine when SRAM_DTC which is non-cached memory is set to Heap's region.

On the other hand, when NCACHE_SDRAM, which is also non-cached memory, is set to Heap's region, it does not work fine.

what is the reason?

Thanks for your cooperation.

[atm2024]

I was able to do it by browsing the URL and making the following changes
https://community.nxp.com/t5/tkb/articleprintpage/tkb-id/imxrt%40tkb/article-id/138
https://www.nxp.com.cn/docs/en/application-note/AN12042.pdf
> enet_ethernetif_kinetis.c : SDK_ALIGN to AT_NONCACHEABLE_SECTION_ALIGN
> Heap's region : Default to SRAM_DTC

After that, I changed from SRAM_DTC to NCACHE_REGION and it stopped working properly.
change parts:
> Heap's region
> *(NonCacheable.init)'s region
> *(NonCacheable)'s region

What is the difference between SRAM_DTC and NCACHE_REGION?

Thanks in advance.

[Omar_Anguiano]

DTCM/ITCM is Tightly-Coupled Memories, they are near the core so they can access it directly (cache is not involved) while the NCACHE_REGION is field on memory that can be cacheable but it is configured to be non-cache. 

Best regards,
Omar