Hello, i have a problem in ADC1 group B configuration using MKV31F256 device and MCUXpresso SDK

[dhaferhannaoui]

Hello, i have a problem in ADC group B configuration using MKV31F256 device and MCUXpresso SDK.

So in my project, the adc1 SE18 channel is configured as group B, and it's triggered using PDB hardware trigger, but the adc conversion didn't start, also i tried to use ADC0, but the same problem.

But when i used the same project but with changing adc1 SE18 channel as group A, the program woks well (adc conversion starts well).

So,I want that the project works also with group B, because i need to use 4 ADC channels in the real project (using adc1(with two channels) and adc0(with two channels)).

you find attached the project and the detailled project description in the main file.

faithfully,

Original Attachment has been moved to: adc_SE18_Groupe_B_Pdb_hw_trig.rar

[xiangjun_rong]

Hi, Dhafer,

I see your problem. For ADC0 and ADC1 modules of KV31, only analog channels ADCx_SE4/5/6/7 channels can select a or b channel by configuring the ADCx_CFG2[MUXSEL] bit, for the other analog channel, there is not option, you have to clear the ADCx_CFG2[MUXSEL] bit or select Group A.

Hope it can help you

BR

Xiangjun Rong

[dhaferhannaoui]

Hi, 

thank you for your response.

So i tried to configure ADC0_SE4b, but it's the same problem, no conversion start.

You can see attached the new program and pictures of registers state of PDB0 and ADC0 when i tested the new program located in this link : http://new_program_with_ADC0_SE4_b

Thank you.

BR.

Dhafer HANNAOUI

[xiangjun_rong]

Hi, Dhafer,

I have three questions for the register setting of both PDB and ADC converter.

Firstly, for ADC, you  set the ADC0_SC1A as 0x1F, if the ADCH bits is 5b'11111, the ADC is disabled, pls change the ADCH bits to a valid channel.

Secondly, MUXSEL bits take effect on the both ADC0_SC1A and ADC0_SC1B channel.

Thirdly, pls check the PDB0_CH0S, the LSB of the register is set, which means that the ADC sampling has error, you should clear the bit so that the PDB can work after error happens. The triggering interval between two sampling must be greater than ADC conversion time.

BR

Xiangjun Rong

[dhaferhannaoui]

Hi, 

Thank you for your answer.

So in my program i configured ADC0 channel 4 as group B (ADC0_SE4b), so in the last pictures  ADC0_SC1B is set as 0x00000044 ( ADCH = 0x04), so the valid channel is selected.

And according to the ADC sampling error, i tested the same code but with configuring  ADC0 channel 4 as group A (instead of  group  B) (ADC0_SC1A as 0x00000044 ), so the LSB of PDB0_CH0S isn't set, so i think that i don't have problem in ADC sampling and conversion time.

you can see attached pictures of the register state (PDB0 and ADC0) after configuring ADC0 channel 4 as group A.

thank you.

BR

[xiangjun_rong]

Hi,

In the register setting, I do not know why you set the ADC0_SC1B as 0x1F, when you set the ADCH bits as 0x1F, the ADC module will be disabled. If you do not want to get the second sample, you can set a valid channel and ignore the sample result in software, it is okay.

BR

XiangJun Rong