I believe there is a potential issue in LPSPI_MasterTransferBlocking() (as found in fsl_lpspi.c / SDK 2.6, MKE14F512VLL16). What I have observed is that if this function is preempted/interrupted for a substantial length of time at the wrong time, an overrun can occur in the Rx FIFO which causes the function to get stuck in an endless loop and never return.
The issue appears to reside in the Tx loop, and is exposed in the following circumstance:
Precondition: The Tx FIFO is full, and the Rx FIFO is still empty (i.e. we are waiting for data to be clocked out)
1. The code waits for room to open up in the Tx FIFO.
2. Once room is available (note that the Rx FIFO will not be empty at this point), another word is written to the Tx FIFO.
3. The code then checks the Rx FIFO, and reads any data that is available.
IF the driver is interrupted for a substantial amount of time between steps (2) and (3) above, it is possible that FIFOSIZE + 1 words will be clocked out before we read anything. If this happens, an Rx FIFO overrun will occur and a word will be dropped. This drop will cause the Rx loop at the end of the function (not shown) to never complete, because rxRemainingByteCount will never reach zero.
I think that switching the order of steps (2) and (3) above would address this issue, as shown in the below snippet. Notice that the write step was moved from before the read step to after the read step:

Thank you.