Putting large buffers in external SDRAM

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Putting large buffers in external SDRAM

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jeffthompson
Contributor V

I want to place large data buffers in external on-board SDRAM. I already have a 4 MB .noinit section there for new fimware downloads, which I created this way:

 

__NOINIT(BOARD_SDRAM_NONCACHEABLE) __attribute__ ((aligned)) uint8_t httpsResponseBody[ 4 * 1024 * 1024 ];

 

Now I want another, smaller buffer (16 kB) and tried

 

__BSS(BOARD_SDRAM_CACHEABLE) __attribute__ ((aligned)) uint8_t assetsEscrow[ 16 * 1024 ];

 

But the linker complains

 

c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/bin/ld.exe: F1721_KAS.axf section `.bss_RAM5' will not fit in region `SRAM_OC'
c:/nxp/mcuxpressoide_11.3.0_5222/ide/plugins/com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/bin/ld.exe: region `SRAM_OC' overflowed by 3541460 bytes

 

Here's my memory map:

jeffthompson_0-1614011902421.png

I've read the chapter in the IDE (MCUXpresso IDE v11.3.0 [Build 5222] [2021-01-11])
User Guide on Memory Configuration and Linker Scripts, but I can't seem to specify that I want assetsEscrow to go into BOARD_SDRAM_CACHEABLE.

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converse
Senior Contributor IV

It is very difficult to tell with the small snippets you have provided, but the linker is not complaining about BOARD_SDRAM_CACHEABLE, but about SRAM_OC (aka RAM5), so there must be something else in your code that is causing some data to be placed there.

 

I also see that your have defined BOARD_SDRAM_CACHEABLE as your first RAM block. This makes it the default RAM block, so is where all of you standard program data will be placed. If this is not what you want, you will need to sort the defined order of your RAM blocks.

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converse
Senior Contributor IV

It is very difficult to tell with the small snippets you have provided, but the linker is not complaining about BOARD_SDRAM_CACHEABLE, but about SRAM_OC (aka RAM5), so there must be something else in your code that is causing some data to be placed there.

 

I also see that your have defined BOARD_SDRAM_CACHEABLE as your first RAM block. This makes it the default RAM block, so is where all of you standard program data will be placed. If this is not what you want, you will need to sort the defined order of your RAM blocks.

View solution in original post

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