PWM module in MKV46F256VLL16

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PWM module in MKV46F256VLL16

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soaring_sun
Contributor III

Hi, 

I have gone through the reference modules and the datasheet of the micro MKV46F256VLL16. But I'm not able to understand how VAL1 to VAL5 are set if I'm using inbuilt functions? What if I have to change those values that are present in the built functions?

Capture.PNG

I have gone through the example code that explains nano edge PWM, but I have a few doubts in them. I am hoping that someone would help me clear it out.

https://community.nxp.com/t5/Kinetis-Microcontrollers/Nano-edge-placement-feature-for-eFlexPWM-modul... 

How will I be able to set FRACVAL if I'm using the inbuilt functions? Along with the PWM block, should I be using the SIM, MCG and PMC modules? Instead of 3.2GHz if I want 5GHz, which module should be changed?

In the inbuilt funciton, SIM_PWRC_SRPWRRDY(x); what does x mean? How much value should I be putting to it?

Thanks in advance

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3 Replies

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soaring_sun
Contributor III

Hello @jingpan, I understand but it is still not clear for me and I have a few questions regarding the same.

1. When you say "use PWM_UpdatePwmDutycycle() to change VAL2~5 directly." which Value will I be changing in VAL2 to VAL5 when I call the example function below?

PWM_UpdatePwmDutycycle(PWMA, kPWM_Module_0, kPWM_PwmA, kPWM_EdgeAligned, 10);

 

2.For the nano edge function, even if we use the config tools, should we be adding the PLLset function in our code? I have tried to use nanoedge PWM using the config tool. For this, I have used FBE mode of operation. I have activated the nanoedge functionality, yet it shows an error. How will I be able to solve this?

The PLLS is selected to operate in PLL mode. The CLKS is configured to output of PLLS. (if this configuration is changed, then the modes vary.) Because of this, I am not able to generate the code.

Screenshot (19).png

 

Please give out a manual which defines what to use in the different modes of operations as it is not clearly stated in the TRM. Thank you

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

1. There last parameter of PWM_UpdatePwmDutycycle()  pwmVal is the percentage of PWM duty cycle. 

2.  FBE is PLL bypassed external mode, it use external clock to Past Peripheral clock directly. But the nanoedge 2x clock must be equal to 2x fast peripheral clock. Please see section 6.5.1 in RM. So, if you want to use nanoedge fucntion, you can't use PBE mode.

jingpan_2-1614321158797.png

 

jingpan_1-1614321056941.png

jingpan_0-1614321024503.png

 

Regards,

Jing

 

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jingpan
NXP TechSupport
NXP TechSupport

Hi soaring_sun,

1. VAL0/1 control period and VAL2~5 control dutycycle. In the driver, it use PWM_DRV_Init3PhPwm() function to set period and dutycycle. The data is saved in pwmSignal structure. When change dutycycle, it use PWM_UpdatePwmDutycycle() to change VAL2~5 directly.
2.But the driver is not cover nanoedge function. Customer have to add this function code by themselves.
3. You can only get 3.2G. Because the fractional delay logic can only be used when the IPBus clock is running at 100 MHz.
4. x is the bit value you want to write into this register, it's 0 or 1.

 

Regards,

Jing

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